Background calibration of offsets in interleaved analog to digital converters

Abstract

A multi-channel time interleaved ADC (TIADC) provides for offset estimation and correction. The correction is accomplished through analog adjustment of offset rather than by digital correction of their outputs. In certain aspects, polarity reversal circuits may be used to further improve performance.

1 . A method for correcting an offset error in an analog to digital converter comprising:
 sampling an analog input signal to provide a sampled analog input signal;   digitizing the sampled analog signal to provide a digitized signal;   pseudo-randomly changing a polarity of the analog input signal;   estimating a Direct Current (DC) offset error from the digitized signal; and   prior to completion of at least one of the sampling step or digitizing step,   adjusting an analog signal to compensate for the DC offset error.   
     
     
         2 . The method of  claim 1  wherein the step of pseudo-randomly changing the polarity of the analog input signal is performed at a rate related to a sampling rate used in the sampling step. 
     
     
         3 . The method of  claim 2  additionally comprising:
 pseudo-randoming changing a polarity of the digitized signal. 
 
     
     
         4 . The method of  claim 3  wherein the step of pseudo-randomly changing a polarity of the digitized signal is performed at a rate that depends on a rate of pseudo-randomly changing a polarity of the analog input signal. 
     
     
         5 . The method of  claim 1  additionally comprising:
 a second step of sampling the analog input signal to provide a second sampled analog signal, with the second step taking samples of the analog input signal at different times than samples taken by the other sampling step. 
 
     
     
         6 . The method of  claim 1  additionally comprising:
 digitizing the second sampled analog signal to provide a second digitized signal; and 
 estimating the Direct Current (DC) offset from both the digitized signal and the second digitized signal. 
 
     
     
         7 . The method of  claim 6  wherein the adjusting step adjusts one of the sampled analog signal or the second sampled analog signal. 
     
     
         8 . The method of  claim 6  wherein the adjusting step adjusts an analog signal generated during one of the digitizing step or the second digitizing step. 
     
     
         9 . The method of  claim 6  wherein the step of estimating additionally comprises:
 integrating at least one of the digitized signal or the second digitized signal, to produce an averaged digital signal. 
 
     
     
         10 . The method of  claim 9  additionally comprising, between the step of estimating and adjusting,
 converting a digital DC offset error estimate derived from the averaged digital signal to an analog DC offset error estimate signal. 
 
     
     
         11 . An analog to digital converter apparatus comprising:
 a sampler, for providing a sampled analog signal from an input analog signal;   a digitizer, operating on the sampled analog signal to produce a digitized signal having M bits of resolution;   an input signal analog chopper, for pseudo-randomly changing a polarity of the analog input signal;   an accumulator, for accumulating samples of the digitized signal, to produce a digital Direct Current (DC) offset error signal;   a digital to analog converter, for converting the digital DC offset error signal, to produce an analog DC offset error signal; and   a combiner, disposed prior to, or within, at least one of the sampler or digitizer, for combining the analog DC offset error signal with an analog signal to compensate for offset error in the apparatus.   
     
     
         12 . The apparatus of  claim 11  additionally comprising:
 a second sampler, for providing a second sampled analog signal from the input analog signal; and 
 a second digitizer, operating on the sampled analog signal to produce a second digitized signal having M bits of resolution. 
 
     
     
         13 . The apparatus of  claim 11  additionally wherein:
 an accumulator and a combiner arranged to process each of the digitized signal and the second digitized signal. 
 
     
     
         14 . The apparatus of  claim 13  wherein the combiner operates on the analog input signal. 
     
     
         15 . The apparatus of  claim 13  wherein the combiner operates on the sampled analog signal. 
     
     
         16 . The apparatus of  claim 13  wherein the combiner operates on an analog signal generated within the digitizer. 
     
     
         17 . The apparatus of  claim 11  wherein the accumulator produces an averaged digital signal to be used as the digital DC offset error signal. 
     
     
         18 . The apparatus of  claim 11  wherein input signal analog chopper pseudo-randomly changes the polarity of the analog input signal at a rate related to a sampling rate used by the sampler. 
     
     
         19 . The apparatus of  claim 18  additionally comprising:
 an output signal digital chopper, for pseudo-randoming changing a polarity of the digitized signal. 
 
     
     
         20 . The apparatus of  claim 19 , additionally comprising:
 a delay circuit, for adjusting a relative delay in the operation of the input signal analog chopper and output signal digital chopper, to compensate for operations by the sampler and digitizer.   
     
     
         21 . The apparatus of  claim 12  wherein the accumulator further comprises:
 a digital integrator, for accumulating samples of one of the digitized signal or the second digitized signal, to produce the digital DC offset error signal. 
 
     
     
         22 . The apparatus of  claim 12  wherein the accumulator further comprises:
 a second digital to analog converter, for converting one of the digitized signal or the second digitized signal, to produce an analog converter output signal; and 
 an analog integrator, for accumulating samples of the analog converter output signal, to produce the analog DC offset error signal.