Printed circuit board and layout method thereof

Abstract

A printed circuit board includes first and second layout layers, first and second components, and a pair of connecting portions. The first layout layer includes a pair of first conducting portions connected to a control chip. The second layout layer includes pairs of second to fourth conducting portions. The connecting portions connect the first and third conducting portions together. When an electronic device is connected to the second conducting portions, and the first and second components are connected to the third and fourth conducting portions to form a first route, signals generated by the control chip are transmitted to the electronic device through the first route. When the electronic device is connected to the fourth conducting portions, and the first and second components are connected to the second and third conducting portions to form a second route, the signals are transmitted to the electronic device through the second route.

1 . A printed circuit board (PCB), comprising:
 a first layout layer and a second layout layer;   a control chip;   a pair of first conducting portions positioned on the first layout layer and electrically connected to the control chip; and   a pair of second conducing portions, a pair of third conducting portions, and a pair of fourth conducting portions positioned on the second layout layer;   a pair of connecting portions electrically connecting the first conducting portions of the first layout layer to the third conducting portions of the second layout layer; and   a first component and a second component;   wherein in response to an electronic device being electrically connected to the second conducting portions, the first component electrically connecting one of the second conducting portions to a corresponding one of the third conducting portions, and the second component electrically connecting the other one of the second conducting portions to the other one of the third conducting portions, such that a pair of high-speed differential signals generated by the control chip is transmitted to the electronic device, through the first conducting portions, the connecting portions, the third conducting portions, the first and second components, and the second conducting portions in turn; and   wherein in response to the electronic device being electrically connected to the fourth conducting portions, the first component electrically connecting one of the fourth conducting portions to a corresponding one of the third conducting portions, and the second component electrically connecting the other one of the fourth conducting portions to the other one of the third conducting portions, such that the pair of high-speed differential signals is transmitted to the electronic device, through the first conducting portions, the connecting portions, the third conducting portions, the first and second components, and the fourth conducting portions in turn.   
     
     
         2 . The PCB of  claim 1 , wherein the connecting portions are a pair of vias. 
     
     
         3 . The PCB of  claim 1 , wherein the connecting portions are a pair of embedded vias. 
     
     
         4 . The PCB of  claim 1 , wherein the first component and the second component are resistors. 
     
     
         5 . The PCB of  claim 1 , wherein the first component and the second component are capacitors. 
     
     
         6 . The PCB of  claim 5 , wherein each capacitor is an alternating current coupling capacitor. 
     
     
         7 . The PCB of  claim 1 , wherein the pair of second conducting portions, the pair of third conducting portions and the pair of fourth conducting portions are arranged on the second layout layer in corresponding linear alignments. 
     
     
         8 . A printed circuit board (PCB) layout method, comprising:
 providing a PCB comprising a first layout layer and a second layout layer;   positioning a pair of first conducting portions on the first layout layer to electrically couple to a control chip;   positioning a pair of second conducting portions, a pair of third conducting portions, and a pair of fourth conducting portions on the second layout layer;   providing a pair of connecting portions to electrically connect the first conducting portions of the first layout layer to the third conducting portions of the second layout layer;   electrically connecting an electronic device to the second conducting portions, and providing a first component to electrically connect one of the second conducting portions to a corresponding one of the third conducting portions, and a second component to electrically connect the other one of the second conducting portions to the other one of the third conducting portions to form a first route; or electrically connecting the electronic device to the fourth conducting portions, and providing the first component to electrically connect one of the fourth conducting portions to a corresponding one of the third conducting portions, and the second component to electrically connect the other one of the fourth conducting portions to the other one of the third conducting portions to form a second route; and   transmitting a pair of high-speed differential signals generated by the control chip to the electronic device, through the first conducting portions, the connecting portions, the third conducting portions, the first and second components, and the second conducting portions in turn in response to the first route being formed, or through the first conducting portions, the connecting portions, the third conducting portions, the first and second components, and the fourth conducting portions in turn in response to the second route being formed.   
     
     
         9 . The method of  claim 8 , wherein the connecting portions are a pair of vias. 
     
     
         10 . The method of  claim 8 , wherein the connecting portions are a pair of embedded vias. 
     
     
         11 . The method of  claim 8 , wherein each of the first component and the second component is a resistor. 
     
     
         12 . The method of  claim 8 , wherein each of the first component and the second component is a capacitor. 
     
     
         13 . The method of  claim 12 , wherein each capacitor is an alternating current coupling capacitor. 
     
     
         14 . The method of  claim 8 , wherein in the positioning a pair of second conducting portions, a pair of third conducting portions, and a pair of fourth conducting portions on the second layout layer step, the pair of second conducting portions, the pair of third conducting portions and the pair of fourth conducting portions are arranged on the second layout layer in corresponding linear alignments.