Dma controller

Abstract

The DMA controller includes a peripheral device read unit to read states of peripheral devices, a state comparator, a transfer unit, a register, and a peripheral device write unit to write data in the peripheral devices according to the contents in the register when the DMA transfer is executed, an interrupt select unit selects one of plural interrupt signals to determine whether the peripheral device read unit, the state comparator and the transfer unit are at a timing to execute operations. Based on these operations the state comparator determines whether to start the DMA transfer, and the transfer unit executes data transfer between the peripheral devices.

1 . A DMA controller comprising:
 a peripheral device read unit for reading states of a plurality of peripheral devices to acquire the states of the plurality of peripheral devices, wherein each peripheral device includes a register;   a state comparator;   a transfer unit for executing a DMA transfer; and   a content register including contents to operate the peripheral device read unit, the state comparator, and the transfer unit to execute DMA transfer;   a peripheral device write unit for writing data in each register of the peripheral devices according to the contents in the content register when the DMA transfer is executed or the DMA transfer is finished for performing control of the peripheral devices or notification of information to the peripheral devices;   an interrupt select unit;   a counter for measuring a time;   a counter comparator for comparing a value of the counter and a counter value indicating an estimated time of DMA transfer; and   an interrupt/cycle-operation select unit,   wherein, the interrupt select unit is configured for receiving a plurality of interrupt signals and for selecting one of the interrupt signals among the plurality of interrupt signals,   wherein the interrupt/cycle-operation select unit is configured to determine whether the peripheral device read unit, the state comparator and the transfer unit are at a timing to execute operations according to either the interrupt signal selected by the interrupt select unit or establishment of a comparison result by the counter comparator,   wherein, at the timing determined by the interrupt/cycle-operation select unit determined, the peripheral device read unit reads the states of the plurality of peripheral devices according to the contents set in the content resister,   wherein the state comparator is configured to determine whether to start the DMA transfer by the transfer unit according to the states of the plurality of peripheral devices and a start condition of the DMA transfer set in the content register, and   wherein, when the state comparator determines to start the DMA transfer, the transfer unit executes data transfer between the peripheral devices.   
     
     
         2 . The DMA controller according to  claim 1 ,
 wherein the peripheral device read unit is configured to repeat read of the states from the peripheral devices until the comparison result by the state comparator is established.   
     
     
         3 . The DMA controller according to  claim 1 , further comprising
 a first register for storing, in accordance with an instruction from a CPU, a pattern of operation contents upon executing the processing of updating the counter value indicating the expected time of the DMA transfer to the next expected time, the read of at least one of the registers of one of the peripheral devices by the peripheral device read unit, the comparison by the state comparator, and the DMA transfer on condition of establishment of the comparison result by the state comparator, with being triggered by establishment of the comparison result by the counter comparator.   
     
     
         4 . The DMA controller according to  claim 3 , further comprising:
 a second register for storing, in accordance with the instruction from the CPU, an access size upon reading at least one of the registers of one of the peripheral devices by the peripheral device read unit; and   a third register for storing, in accordance with the instruction from the CPU, comparison conditions upon comparing the value of the at least one register of the at least one peripheral device and the start condition of the DMA transfer by the state comparator.   
     
     
         5 . The DMA controller according to  claim 4 , further comprising:
 a fourth register for storing, in accordance with the instruction from the CPU, a pattern of a method of adjusting a next cycle upon reading the at least one register of the at least one peripheral device by the peripheral device read unit.   
     
     
         6 . The DMA controller according to  claim 1 , further comprising:
 a first register for storing, in accordance with an instruction from a CPU, an access size upon reading at least one of the registers of at least one of the peripheral devices by the peripheral device read unit; and   a second register for storing, in accordance with the instruction from the CPU, comparison conditions upon comparing the value of the at least one register of the at least one peripheral device and the start condition of the DMA transfer by the state comparator.   
     
     
         7 . The DMA controller according to  claim 4 , further comprising:
 a first register for storing, in accordance with an instruction from the CPU, a pattern of a method of adjusting a next cycle upon reading at least one of the registers of at least one of the peripheral devices by the peripheral device read unit.