Thin film transistor and organic light emitting diode display using the same and method for manufacturing the same

Abstract

A thin film transistor includes an active layer on a substrate and crystallized through growth of crystals due to an action of metal catalysts, a gate insulating layer pattern on a part of the active layer; a gate electrode on a part of the gate insulating layer pattern; an anti-etching layer pattern formed on the gate insulating layer pattern to cover the gate electrode, the anti-etching layer pattern being coextensive with the gate insulating layer pattern; a source electrode and a drain electrode on the active layer and the anti-etching layer pattern; and gettering layer patterns between the active layer and the anti-etching layer pattern and between the source electrode and the drain electrode to eliminate the metal catalysts used for crystallization of the active layer, the gettering layer patterns being coextensive with the source electrode and drain electrode.

1 . A thin film transistor comprising:
 an active layer on a substrate and crystallized through growth of crystals due to an action of metal catalysts;   a gate insulating layer pattern on a part of the active layer;   a gate electrode on a part of the gate insulating layer pattern;   an anti-etching layer pattern formed on the gate insulating layer pattern to cover the gate electrode, the anti-etching layer pattern being coextensive with the gate insulating layer pattern;   a source electrode and a drain electrode on the active layer and the anti-etching layer pattern; and   gettering layer patterns between the active layer and the anti-etching layer pattern and between the source electrode and the drain electrode to eliminate the metal catalysts used for crystallization of the active layer, the gettering layer patterns being coextensive with the source electrode and drain electrode.   
     
     
         2 . The thin film transistor of  claim 1 , wherein the metal catalysts include nickel (Ni) and the gettering layer patterns include titanium (Ti). 
     
     
         3 . The thin film transistor of  claim 1 , wherein:
 an area of the active layer overlapped by the gate electrode is a channel area, and   areas of the active layer at sides of the channel area and contacting the source electrode and the drain electrode are a source area and a drain area respectively.   
     
     
         4 . The thin film transistor of  claim 1 , wherein the anti-etching layer pattern has a different etching selectivity from etching selectivities of the gettering layer patterns, the source electrode, and the drain electrode. 
     
     
         5 . A method for manufacturing a thin film transistor comprising:
 preparing a substrate;   forming an amorphous silicon layer on the substrate;   applying metal catalysts above or below the amorphous silicon layer;   forming a polysilicon layer by crystallizing the amorphous silicon layer through a growth of crystals from an action of the metal catalysts;   forming an active layer by patterning the polysilicon layer;   forming a gate insulating layer on a part of the active layer;   forming a gate electrode on a part of the gate insulating layer;   forming an anti-etching layer covering the gate insulating layer and the gate electrode;   forming a gate insulating layer pattern and an anti-etching layer pattern that are coextensive with each other by patterning the gate insulating layer and the anti-etching layer together;   forming a gettering layer on the active layer and the anti-etching layer pattern;   forming a source-drain metal layer on the gettering layer; and   forming a source electrode, a drain electrode, and a gettering layer pattern by patterning the gettering layer and the source-drain metal layer together.   
     
     
         6 . The method for manufacturing the thin film transistor of  claim 5 , wherein the metal catalysts include nickel (Ni) and the gettering layer pattern includes titanium (Ti). 
     
     
         7 . The method for manufacturing the thin film transistor of  claim 5 , further comprising forming an area of the active layer that is overlapped by the gate electrode as a channel area by doping the active layer with an impurity using the gate electrode as a mask, and forming a source area and a drain area respectively contacting the source electrode and the drain electrode at both sides of the channel area. 
     
     
         8 . The method for manufacturing the thin film transistor of  claim 5 , wherein the anti-etching layer pattern has a different etching selectivity from etching selectivities of the gettering layer, the source electrode, and the drain electrode. 
     
     
         9 . A display device comprising:
 an active layer on a substrate and crystallized through growth of crystals due to an action of metal catalysts;   a gate insulating layer pattern on a part of the active layer;   a gate electrode on a part of the gate insulating layer pattern;   an anti-etching layer pattern formed with a same pattern as the gate insulating layer pattern, the anti-etching layer pattern being formed on the gate insulating layer pattern to cover the gate electrode;   a source electrode and a drain electrode on the active layer and the anti-etching layer pattern; and   gettering layer patterns between the active layer and the anti-etching layer pattern and between the source electrode and the drain electrode to eliminate the metal catalysts used for the crystallization of the active layer, the gettering layer patterns having a same pattern as patterns of the source electrode and the drain electrode, respectively.   
     
     
         10 . The display device of  claim 9 , wherein the metal catalysts include nickel (Ni) and the gettering layer patterns include titanium (Ti). 
     
     
         11 . The display device of  claim 9 , wherein:
 an area of the active layer overlapped by the gate electrode is a channel area, and   areas at both sides of the channel area that respectively contact the source electrode and the drain electrode are a source area and a drain area.   
     
     
         12 . The display device of  claim 9 , further comprising an organic light emitting diode on the substrate and connected with the drain electrode. 
     
     
         13 . The display device of  claim 9 , wherein the anti-etching layer pattern has a different etching selectivity from etching selectivities of the gettering layer, the source electrode, and the drain electrode. 
     
     
         14 . A method for manufacturing a display device comprising:
 preparing a substrate;   forming an amorphous silicon layer on the substrate;   applying metal catalysts above or below the amorphous silicon layer;   forming a polysilicon layer by crystallizing the amorphous layer through growth of crystals from an action of the metal catalysts;   forming an active layer by patterning the polysilicon layer;   forming a gate insulating layer on a part of the active layer;   forming a gate electrode on a part of the gate insulating layer;   forming an anti-etching layer covering the gate insulating layer and the gate electrode;   forming a gate insulating layer pattern and an anti-etching layer pattern that are coextensive with each other by patterning the gate insulating layer and the anti-etching layer together;   forming a gettering layer on the active layer and the anti-etching layer pattern;   forming a source-drain metal layer on the gettering layer; and   forming a source electrode, a drain electrode, and a gettering layer pattern by pattering the gettering layer and the source-drain metal layer together.   
     
     
         15 . The method for manufacturing the display device of  claim 14 , wherein the metal catalysts include nickel (Ni) and the gettering layer pattern includes titanium (Ti). 
     
     
         16 . The method for manufacturing the display device of  claim 14 , further comprising forming an area of the active layer that is overlapped by the gate electrode as a channel area by doping the active layer with an impurity using the gate electrode as a mask, and forming a source area and a drain area respectively contacting the source electrode and the drain electrode at both sides of the channel area. 
     
     
         17 . The method for manufacturing the display device of  claim 14 , further comprising forming an organic light emitting diode connected with the drain electrode on the substrate. 
     
     
         18 . The method for manufacturing the display device of  claim 14 , wherein the anti-etching layer pattern has a different etching selectivity from etching selectivities of the gettering layer, the source electrode, and the drain electrode.