Interlock circuit and interlock system including the same

Abstract

An interlock circuit includes an input delay unit and an output suppressing unit. The input delay unit delays a plurality of input signals, provides a plurality of delayed input signals, and provides a plurality of exclusive input signals by performing a logical operation on the plurality of delayed input signals. The output suppressing unit provides a plurality of output signals, which are not simultaneously enabled, based on the plurality of exclusive input signals and the plurality of input signals.

1 . An interlock circuit comprising:
 an input delay unit that delays a plurality of input signals, provides a plurality of delayed input signals, and provides a plurality of exclusive input signals by performing a logical operation on the plurality of delayed input signals; and   an output suppressing unit that provides a plurality of output signals, which are not simultaneously enabled, based on the plurality of exclusive input signals and the plurality of input signals.   
     
     
         2 . The interlock circuit of  claim 1 , wherein the input delay unit comprises:
 a delay unit comprising a plurality of input delay circuits that respectively delay the plurality of input signals and provide the plurality of delayed input signals; and   an exclusive logical operation unit comprising a plurality of exclusive logical operation circuits that provide the plurality of exclusive input signals by respectively performing exclusive logical operations on the plurality of delayed input signals.   
     
     
         3 . The interlock circuit of  claim 2 , wherein a first exclusive logical operation circuit included in the plurality of exclusive logical operation circuits provides a first exclusive input signal included in the plurality of exclusive input signals by performing an logical AND operation on a first delayed input signal, and complementary signals of delayed input signals other than the first delayed input signal. 
     
     
         4 . The interlock circuit of  claim 2 , wherein a first input delay circuit included in the plurality of input delay circuits comprises:
 a first transistor comprising a gate that receives a first input signal included in the plurality of input signals and a first terminal that receives a power supply voltage;   a first resistor that is connected between a first node and a second terminal of the first transistor;   a second transistor comprising a gate that receives the first input signal, a first terminal that is connected to a ground voltage, and a second terminal that is connected to the first node;   a second resistor that is connected between the first node and a second node; and   a capacitor that is connected between the ground voltage and the second node.   
     
     
         5 . The interlock circuit of  claim 4 , wherein a first delayed input signal included in the plurality of delayed input signals is provided by the second node,
 wherein when the first input signal transitions from logic state “low” to logic state “high” the first delayed input signal is delayed by a predetermined input delay time, and   when the first input signal transitions from logic state “high” to logic state “low”, the first delayed input signal is delayed by a predetermined dead time.   
     
     
         6 . The interlock circuit of  claim 5 , wherein the predetermined input delay time and the predetermined dead time are determined based on the first and second resistors. 
     
     
         7 . The interlock circuit of  claim 6 , wherein the predetermined dead time is longer than the predetermined input delay time. 
     
     
         8 . The interlock circuit of  claim 1 , wherein the output suppressing unit comprises a plurality of output suppressing circuits,
 wherein each of the plurality of output suppressing circuits comprises:   a set circuit that provides a first set signal by performing a logical AND operation based on a first exclusive input signal included in the plurality of exclusive input signals, a first delayed input signal included in the plurality of delayed input signals, and a second complementary input signal corresponding to a complementary signal of a second input signal included in the plurality of input signals;   a reset circuit that provides a first reset signal by performing an OR logical operation on a second output signal and a first complementary input signal corresponding to a complementary signal of the first input signal; and   an output latch circuit that provides a first output signal based on the first set signal and the first reset signal.   
     
     
         9 . The interlock circuit of  claim 8 , wherein the output latch circuit enables the first output signal in response to the first set signal, and disables the first output signal in response to the first reset signal. 
     
     
         10 . The interlock circuit of  claim 1 , wherein the input delay unit comprises:
 a delay unit that receives a first input signal and a second input signal, delays the first input signal and the second input signal by a predetermined delay time, and provides first and second delayed input signals; and   an exclusive logical operation unit that provides first and second exclusive input signals by performing an exclusive logical operation on the first and second delayed input signals, wherein the interlock circuit further comprises a noise removing unit that provides first and second noise suppressed signals based on first and second reset signals, and the first and second delayed input signals, and   wherein the output suppressing unit comprises:   a set unit that provides a first set signal based on the first noise suppressed signal, the first exclusive input signal, and the second input signal, and a second set signal based on the second noise suppressed signal, the second exclusive input signal, and the first input signal;   a reset unit that provides a first reset signal based on the first input signal and a second output signal, and a second reset signal based on the second input signal and a first output signal; and   an output latch unit that provides the first output signal based on the first set signal and the first reset signal, and the second output signal based on the second set signal and the second reset signal.   
     
     
         11 . The interlock circuit of  claim 10 , wherein the noise removing unit comprises:
 a first noise removing latch circuit that enables the first noise suppressed signal in response to the first delayed input signal, and disables the first noise suppressed signal in response to the first reset signal; and   a second noise removing latch circuit that enables the second noise suppressed signal in response to the second delayed input signal, and disables the second noise suppressed signal in response to the second reset signal.   
     
     
         12 . The interlock circuit of  claim 10 , wherein the set unit comprises:
 a first set circuit that provides the first set signal by performing a logical AND operation on the first noise suppressed signal, the first exclusive input signal, and a second complementary input signal corresponding to a complementary signal of the second input signal; and   a second set circuit that provides the second set signal by performing a logical AND operation on the second noise suppressed signal, the second exclusive input signal, and a first complementary input signal corresponding to a complementary signal of the first input signal.   
     
     
         13 . The interlock circuit of  claim 10 , wherein the reset unit comprises:
 a first reset circuit that provides the first reset signal by performing an OR logical operation on the second output signal and a first complementary input signal corresponding to a complementary signal of the first input signal; and   a second reset circuit that provides the second reset signal by performing an OR logical operation on the first output signal and a second complementary input signal corresponding to a complementary signal of the second input signal.   
     
     
         14 . The interlock circuit of  claim 10 , wherein the output latch unit comprises:
 a first output latch circuit enables the first output signal in response to the first set signal and disables the first output signal in response to the first reset signal; and   a second output latch circuit enables the second output signal in response to the second set signal and disables the second output signal in response to the second reset signal.   
     
     
         15 . The interlock circuit of  claim 14 , wherein the first output latch circuit maintains a previous state of the first output signal when both the first set signal and the first reset signal are disabled, and
 the second output latch circuit maintains a previous state of the second output signal when both the second set signal and the second reset signal are disabled.