Solid-state imaging device driving method

Abstract

Photosensitive cells each includes a photodiode ( 1 ), a transfer gate ( 2 ), a floating diffusion layer portion ( 3 ), an amplifying transistor ( 4 ), and a reset transistor ( 5 ). Drains of the amplifying transistors ( 4 ) of the photosensitive cells are connected to a power supply line ( 10 ), and a pulsed power supply voltage (VddC) is applied to the power supply line ( 10 ). Here, a low-level potential (VddC_L) of the power supply voltage has a predetermined potential higher than zero potential. Specifically, by making the low-level potential (VddC_L) higher than channel potentials obtained when a low level is applied to the reset transistors ( 5 ), or channel potentials obtained when a low level is applied to the transfer gates ( 2 ), or channel potentials of the photodiodes ( 1 ), a reproduced image with low noise is read.

1 - 6 . (canceled) 
     
     
         7 . A solid-state imaging device, comprising:
 a photosensitive region having a plurality of photosensitive cells which are two-dimensionally arranged in first and second directions, each photosensitive cell including a photoelectrical conversion element for generating a signal charge corresponding to an intensity of incident light, a transfer transistor for reading the signal charge in the photoelectrical conversion element and transferring the read signal charge to a signal charge detection section, an amplifier transistor for outputting an electrical signal corresponding to changes in potential of the signal charge detection section, and a reset transistor for resetting the potential of the signal charge detection section; and   a line for supplying a selected voltage to a drain of the reset transistor of each photosensitive cell, wherein   the line supplies, as the selected voltage, a first voltage and a second voltage which is lower than the first voltage,   a potential of the second voltage is higher than zero potential, and   a high-level pulse is applied to the reset transistor of a given one of the photosensitive cells to reset the signal charge detection section of said given one of the photosensitive cells within a time period during which the line for controlling a drain voltage of the reset transistor of each photosensitive cell is at the first voltage, and thereafter, the voltage of the line is returned to the first voltage to reset the signal charge in the photoelectrical conversion element of said given one of the photosensitive cells.   
     
     
         8 . A solid-state imaging device, comprising:
 a photosensitive region having a plurality of photosensitive cells which are two-dimensionally arranged in first and second directions, each photosensitive cell including a photoelectrical conversion element for generating a signal charge corresponding to an intensity of incident light, a transfer transistor for reading the signal charge in the photoelectrical conversion dement and transferring the read signal charge to a signal charge detection section, an amplifier transistor for outputting an electrical signal corresponding to changes in potential of the signal charge detection section, and a reset transistor for resetting the potential of the signal charge detection section;   a line for supplying a selected voltage to a drain of the reset transistor of each photosensitive cell;   a plurality of vertical signal lines, each of which is connected to at least one amplifier transistor;   a noise suppression circuit for suppressing noise in signals outputted to the vertical signal lines; and   a horizontal shift register which receives an output of the noise suppression circuit as an input, wherein   the line supplies, as the selected voltage, a first voltage and a second voltage which is lower than the first voltage,   a potential of the second voltage is higher than zero potential, and   the noise suppression circuit operates within a time period during which the first voltage is applied and during which the horizontal shift register is not driven.   
     
     
         9 . The solid-state imaging device according to  claim 7 , wherein
 a potential of a channel which is formed beneath a gate of the reset transistor of said given one of the photosensitive cells when a low-level voltage is applied to the gate of the reset transistor of said given one of the photosensitive cells is lower than the second voltage.   
     
     
         10 . The solid-state imaging device according to  claim 7 , wherein
 a plurality of transfer control lines for controlling gates of the transfer transistors and a plurality of reset control lines for controlling gates of the reset transistors are provided so as to extend in the first direction of the two-dimensional arrangement of the photosensitive cells, and   a plurality of output signal lines are connected to sources of the amplifier transistors in the second direction of the two-dimensional arrangement of the photosensitive cells.   
     
     
         11 . The solid-state imaging device according to  claim 7 , wherein
 the drain of the reset transistor and the drain of the amplifier transistor are connected with each other.   
     
     
         12 . The solid-state imaging device according to  claim 7 , wherein
 the voltage of the line, which is for controlling the drain voltage of the reset transistor of said given one of the photosensitive cells, is fixed at the first voltage for a predetermined time period,   a high-level pulse is applied to the reset transistor of said given one of the photosensitive cells to reset the signal charge detection section of said given one of the photosensitive cells,   a high-level pulse is applied to the transfer transistor of said given one of the photosensitive cells to transfer the signal charge in the photoelectrical conversion element to the signal charge detection section of said given one of the photosensitive cells, and   the voltage of the line is returned to the first voltage to read out the signal change in the photoelectrical conversion element of said given one of the photosensitive cells.   
     
     
         13 . The solid-state imaging device according to  claim 7 , wherein
 one or more signal lines are shared by the photosensitive cells which are adjacent in a vertical scanning direction or a horizontal scanning direction.   
     
     
         14 . The solid-state imaging device according to  claim 7 , wherein
 a first voltage and a second voltage which is lower than the first voltage, are supplied to the line, as the selected voltage, so as to output signals from a selected plurality of the photosensitive cells which are aligned in one row,   a low-level voltage and a high-level voltage are applied to the reset transistor and the transfer transistor included in each of the plurality of the selected photosensitive cells within a time period during which the first voltage is supplied, such that the amplification transistor in each of the selected plurality of the photosensitive cells is in an operational state, and   a low-level voltage and a high-level voltage are applied to the reset transistor included in each of the plurality of the selected photosensitive cells within a time period during which the second voltage is supplied, such that the amplification transistor in each of the selected plurality of the photosensitive cells is in a non-operational state.   
     
     
         15 . The solid-state imaging device according to  claim 8 , wherein
 a potential of a channel which is formed beneath a gate of the reset transistor of said given one of the photosensitive cells when a low-level voltage is applied to the gate of the reset transistor of said given one of the photosensitive cells is lower than the second voltage.   
     
     
         16 . The solid-state imaging device according to  claim 8 , wherein
 a plurality of transfer control lines for controlling gates of the transfer transistors and a plurality of reset control lines for controlling gates of the reset transistors are provided so as to extend in the first direction of the two-dimensional arrangement of the photosensitive cells, and   a plurality of output signal lines are connected to sources of the amplifier transistors in the second direction of the two-dimensional arrangement of the photosensitive cells.   
     
     
         17 . The solid-state imaging device according to  claim 8 , wherein
 the drain of the reset transistor and the drain of the amplifier transistor are connected to each other.   
     
     
         18 . The solid-state imaging device according to  claim 8 , wherein
 the voltage of the line, which is for controlling the drain voltage of the reset transistor of a given one of the photosensitive cells, is fixed at the first voltage for a predetermined time period,   a high-level pulse is applied to the reset transistor of said given one of the photosensitive cells to reset the signal charge detection section of said given one of the photosensitive cells,   a high-level pulse is applied to the transfer transistor of said given one of the photosensitive cells to transfer the signal charge in the photoelectrical conversion element to the signal charge detection section of said given one of the photosensitive cells, and   the voltage of the line is returned to the first voltage to read out the signal change in the photoelectrical conversion element of said given one of the photosensitive cells.   
     
     
         19 . The solid-state imaging device according to  claim 8 , wherein
 one or more signal lines are shared by the photosensitive cells which are adjacent in a vertical scanning direction or a horizontal scanning direction.   
     
     
         20 . The solid-state imaging device according to  claim 8 , wherein
 a first voltage and a second voltage which is lower than the first voltage, are supplied to the line, as the selected voltage, so as to output signals from a selected plurality of the photosensitive cells which are aligned in one row,   a low-level voltage and a high-level voltage are applied to the reset transistor and the transfer transistor included in each of the plurality of the selected photosensitive cells within a time period during which the first voltage is supplied, such that the amplification transistor in each of the selected plurality of the photosensitive cells is in an operational state, and   a low-level voltage and a high-level voltage are applied to the reset transistor included in each of the plurality of the selected photosensitive cells within a time period during which the second voltage is supplied, such that the amplification transistor in each of the selected plurality of the photosensitive cells is in a non-operational state.