Ldpmos structure for enhancing breakdown voltage and specific on resistance in bicmos-dmos process

Abstract

An LDPMOS structure having enhanced breakdown voltage and specific on-resistance is described, as is a method for fabricating the structure. A P-field implanted layer formed in a drift region of the structure and surrounding a tightly doped drain region effectively increases breakdown voltage while maintaining a relatively low specific on-resistance.

1 . A method, comprising:
 forming a buried layer in a first-conductivity type substrate;   depositing an epitaxial layer of the first conductivity type over the substrate and the buried layer;   forming first and second wells of a second conductivity type in the epitaxial layer;   forming a third well of the first conductivity type between the first and second wells;   forming a field region of the first conductivity type in the third well, the field region being spaced apart from the first and second wells and the buried layer; and   forming a. drain region of the first conductivity type in the field region.   
     
     
         2 . The method as set forth in  claim 1 , wherein:
 the first conductivity type is P-type;   the second conductivity type is N-type; and   the forming of a field region is preceded by driving in the first, second, and third wells.   
     
     
         3 . The method as set forth in  claim 1 , wherein:
 the first conductivity type is N-type;   the second conductivity type is P-type; and   the forming of a field region is preceded by driving in the first, second, and third wells.   
     
     
         4 . The method as set forth in  claim 1 , wherein:
 the buried layer is formed of material having the second conductivity type;   the forming of the first and second wells comprises implanting atoms of the second conductivity type into a surface of the epitaxial layer; and   the forming of the third well comprises implanting atoms of the first conductivity type into the surface of the epitaxial layer.   
     
     
         5 . The method as set forth in  claim 4 , wherein the forming of the first, second, and third wells further comprises driving the wells to a depth about the same as that of an upper extent of the buried layer. 
     
     
         6 . The method as set forth in  claim 1 , further comprising:
 forming a first insulation layer overlying a portion of the second well, a portion of the third well, and a portion of the field region; and   forming a second insulation layer overlying a portion of the first well, a portion of the third well, and a portion of the field region, the first insulation layer being separated from the second insulation layer.   
     
     
         7 . The method as set forth in  claim 6 , wherein the forming of the first and second insulation layers comprises:
 depositing an oxide layer; and   patterning and etching the oxide layer.   
     
     
         8 . The method as set forth in  claim 6 , wherein the forming of the first and second insulation layers comprises local oxidation of silicon. 
     
     
         9 . The method as set forth in  claim 1 , further comprising:
 forming a lightly doped drain region of the first conductivity type in the field region in a space between the first and second insulation regions; and   forming a source region in a surface of the second well.   
     
     
         10 . The method as set forth in  claim 6 , wherein the forming of the source region comprises:
 forming a first region having the second conductivity type; and   forming a second region having the first conductivity type.   
     
     
         11 . A semiconductor structure fabricated according to the method set forth in  claim 1 .