Prefetch Unit

Abstract

In one embodiment, a processor comprises a prefetch unit coupled to a data cache. The prefetch unit is configured to concurrently maintain a plurality of separate, active prefetch streams. Each prefetch stream is either software initiated via execution by the processor of a dedicated prefetch instruction or hardware initiated via detection of a data cache miss by one or more load/store memory operations. The prefetch unit is further configured to generate prefetch requests responsive to the plurality of prefetch streams to prefetch data in to the data cache.

1 . A processor comprising:
 a data cache configured to store a plurality of cache blocks;   a memory request buffer configured to store requests for memory operations that miss in the data cache to be transmitted to memory; and   a prefetch unit configured to generate a prefetch request to prefetch a cache block into the data cache, wherein the prefetch unit is configured to detect whether or not the prefetch request hits in the memory request buffer, and wherein the prefetch unit is configured to cancel the prefetch request responsive to a hit in the memory request buffer.   
     
     
         2 . The processor as recited in  claim 1  wherein the hit in the memory request buffer is detected for the prefetch request responsive to a match between the address of the cache block being prefetched and an address queued in the memory request buffer to be fetched from memory. 
     
     
         3 . The processor as recited in  claim 2  wherein the address queued in the memory request buffer is for a non-prefetch request. 
     
     
         4 . The processor as recited in  claim 3  wherein the address is a cache fill for a cache miss. 
     
     
         5 . The processor as recited in  claim 1  wherein the prefetch unit is further configured to detect whether or not the prefetch request hits in the data cache, and wherein the prefetch unit is configured to cancel the prefetch request responsive to a hit in the data cache. 
     
     
         6 . A method comprising:
 a prefetch unit generating a prefetch request to prefetch a cache block into a data cache;   the prefetch unit detecting that the prefetch request hits in a memory request buffer that is configured to store requests for memory operations that miss in the data cache to be transmitted to memory; and   the prefetch unit terminating the prefetch request responsive to the hit in the memory request buffer.   
     
     
         7 . The method as recited in  claim 6  wherein the hit in the memory request buffer is detected for the prefetch request responsive to a match between the address of the cache block being prefetched and an address queued in the memory request buffer to be fetched from memory. 
     
     
         8 . The method as recited in  claim 7  wherein the address is a cache fill for a cache miss. 
     
     
         9 . The method as recited in  claim 6  further comprising:
 the prefetch unit detecting that a second prefetch request hits in the data cache; and 
 the prefetch unit terminating the second prefetch request responsive to the hit in the data cache. 
 
     
     
         10 . A processor comprising:
 a data cache configured to store a plurality of cache blocks;   a memory request buffer configured to store requests for memory operations to be transmitted to memory; and   a prefetch unit configured to generate a prefetch request to prefetch a cache block into the data cache, wherein the prefetch unit is configured to cancel the prefetch request responsive to a hit in the memory request buffer by the prefetch request.   
     
     
         11 . The processor as recited in  claim 10  wherein the hit in the memory request buffer is detected for the prefetch request responsive to a match between the address of the cache block being prefetched and an address queued in the memory request buffer to be fetched from memory. 
     
     
         12 . The processor as recited in  claim 11  wherein the address queued in the memory request buffer is for a non-prefetch request. 
     
     
         13 . The processor as recited in  claim 12  wherein the address is a cache fill for a cache miss. 
     
     
         14 . The processor as recited in  claim 10  wherein the prefetch unit is further configured to detect whether or not the prefetch request hits in the data cache, and wherein the prefetch unit is configured to cancel the prefetch request responsive to a hit in the data cache. 
     
     
         15 . A method comprising:
 a prefetch unit generating a prefetch request to prefetch a cache block into a data cache; and   the prefetch unit canceling the prefetch request responsive to the hit in the memory request buffer.   
     
     
         16 . The method as recited in  claim 15  further comprising:
 the prefetch unit detecting that the prefetch request hits in a memory request buffer that is configured to store requests for memory operations that miss in the data cache to be transmitted to memory. 
 
     
     
         17 . The method as recited in  claim 16  wherein a hit in the memory request buffer is detected for the prefetch request responsive to a match between the address of the cache block being prefetched and an address queued in the memory request buffer to be fetched from memory. 
     
     
         18 . The method as recited in  claim 17  wherein the address is a cache fill for a cache miss. 
     
     
         19 . The method as recited in  claim 15  further comprising:
 the prefetch unit detecting that a second prefetch request hits in the data cache; and 
 the prefetch unit terminating the second prefetch request responsive to the hit in the data cache.