Semiconductor memory device

Abstract

In a static random access memory (SRAM) device having a hierarchical bit line architecture, a local sense amplifier (SA) circuit includes P-channel transistors which precharge local bit lines connected to memory cells, P-channel transistors each having a gate connected to a corresponding one of the local bit lines and a drain connected to a corresponding one of global bit lines, and N-channel transistors each having a gate connected to a corresponding one of the global bit lines and a drain connected to a corresponding one of the local bit lines. As a result, restore operation to a non-selected memory cell during write operation can be achieved without the need of a fine timing control, the speed of read operation by a feedback function can be increased, and the area can be reduced.

1 . A semiconductor memory device comprising:
 a first and a second signal line forming a pair of signal lines;   a third and a fourth signal line forming another pair of signal lines;   a memory cell connected to the first and second signal lines; and   a sense amplifier circuit provided between the first and second signal lines and the third and fourth signal lines,   
       wherein
 the sense amplifier circuit includes
 a first transistor of a first conductivity type having a gate connected to a precharge signal, a source connected to a first power supply potential, and a drain connected to the first signal line, 
 a second transistor of the first conductivity type having a gate connected to the precharge signal, a source connected to the first power supply potential, and a drain connected to the second signal line, 
 a third transistor of the first conductivity type having a gate connected to the first signal line, a source connected to the first power supply potential, and a drain connected to the third signal line, 
 a fourth transistor of the first conductivity type having a gate connected to the second signal line, a source connected to the first power supply potential, and a drain connected to the fourth signal line, 
 a fifth transistor of a second conductivity type having a gate connected to the third signal line, a source connected to a second power supply potential, and a drain connected to the first signal line, and 
 a sixth transistor of the second conductivity type having a gate connected to the fourth signal line, a source connected to the second power supply potential, and a drain connected to the second signal line. 
 
 
     
     
         2 . The semiconductor memory device of  claim 1 , wherein
 the first and second signal lines are local bit lines,   the third and fourth signal lines are global bit lines,   the local and global bit lines form a hierarchical bit line architecture.   
     
     
         3 . The semiconductor memory device of  claim 1 , wherein the memory cell includes
 a first cell transistor of the first conductivity type having a source connected to the first power supply potential, a drain connected to a first memory node, and a gate connected to a second memory node,   a second cell transistor of the first conductivity type having a source connected to the first power supply potential, a drain connected to the second memory node, and a gate connected to the first memory node,   a third cell transistor of the second conductivity type having a source connected to the second power supply potential, a drain connected to the first memory node, and a gate connected to the second memory node,   a fourth cell transistor of the second conductivity type having a source connected to the second power supply potential, a drain connected to the second memory node, and a gate connected to the first memory node,   a fifth cell transistor of the second conductivity type having a source connected to the first memory node, a drain connected to the first signal line, and a gate connected to a word line, and   a sixth cell transistor of the second conductivity type having a source connected to the second memory node, a drain connected to the second signal line, and a gate connected to the word line.   
     
     
         4 . The semiconductor memory device of  claim 1 , wherein the memory cell includes
 a first cell transistor of the first conductivity type having a source connected to the first power supply potential, a drain connected to a first memory node, and a gate connected to a second memory node,   a second cell transistor of the first conductivity type having a source connected to the first power supply potential, a drain connected to the second memory node, and a gate connected to the first memory node,   a third cell transistor of the second conductivity type having a source connected to the second power supply potential, a drain connected to the first memory node, and a gate connected to the second memory node,   a fourth cell transistor of the second conductivity type having a source connected to the second power supply potential, a drain connected to the second memory node, and a gate connected to the first memory node,   a fifth cell transistor of the second conductivity type having a source connected to the first memory node, a drain connected to the first signal line, and a gate connected to a first word line, and   a sixth cell transistor of the second conductivity type having a source connected to the second memory node, a drain connected to the second signal line, and a gate connected to a second word line different from the first word line.   
     
     
         5 . The semiconductor memory device of  claim 1 , wherein the sense amplifier circuit further includes
 a seventh transistor of the second conductivity type having a drain connected to the sources of the fifth and sixth transistors, a source connected to the second power supply potential, and a gate connected to a control signal derived from a column selection signal.   
     
     
         6 . The semiconductor memory device of  claim 1 , wherein
 the potential value of the second power supply potential connected to the sources of the fifth and sixth transistors is controlled based on a control signal derived from a column selection signal.   
     
     
         7 . A semiconductor memory device comprising:
 memory cells;   bit lines each connected to corresponding ones of the memory cells; and   sense amplifier circuits each connected to corresponding ones of the bit lines,   
       wherein
 each of the sense amplifier circuits has a single-end configuration and a function of writing data read from a corresponding one of the memory cells back to the corresponding bit lines, and achieves data write operation to a corresponding one of the memory cells by the function of writing data back to the corresponding bit lines. 
 
     
     
         8 . The semiconductor memory device of  claim 7 , wherein
 the bit lines have a hierarchical architecture divided in memory cell arrays.   
     
     
         9 . The semiconductor memory device of  claim 7 , wherein
 the function of writing data back to the bit line is a function of writing back one of high data and low data.   
     
     
         10 . The semiconductor memory device of  claim 7 , wherein
 each of the sense amplifier circuits is provided between separated memory cell arrays.   
     
     
         11 . The semiconductor memory device of  claim 10 , wherein
 two of the sense amplifier circuits connected to two separated ones of the bit lines are arranged adjacent to each other.