Semiconductor Device with Low-Conducting Field-controlling Element

Abstract

A semiconductor device including a low conducting field-controlling element is provided. The device can include a semiconductor including an active region (e.g., a channel), and a set of contacts to the active region. The field-controlling element can be coupled to one or more of the contacts in the set of contacts. The field-controlling element can be formed of a low conducting layer of material and have a lateral resistance that is both larger than an inverse of a minimal operating frequency of the device and smaller than an inverse of a maximum control frequency of the device.

1 . A device comprising:
 a semiconductor including an active region;   a set of contacts to the active region; and   a field-controlling element located on a first side of the active region, wherein a lateral resistance of the field-controlling element is larger than an inverse of a minimal operating frequency of the device and the lateral resistance of the field-controlling element is smaller than an inverse of a maximum control frequency of the device.   
     
     
         2 . The device of  claim 1 , wherein the field-controlling element is formed of one of: a semiconductor material; a semimetal material; or a dielectric material. 
     
     
         3 . The device of  claim 1 , wherein the device includes a set of field-controlling elements, and wherein the set of field-controlling elements covers substantially all of an area corresponding to the active region. 
     
     
         4 . The device of  claim 1 , wherein the field-controlling element is electrically coupled to the at least one of the set of contacts. 
     
     
         5 . The device of  claim 1 , wherein the field-controlling element is capacitively coupled to the at least one of the set of contacts. 
     
     
         6 . The device of  claim 1 , wherein the field-controlling element is a layer located in an epitaxial structure of the device within one micrometer from the active region. 
     
     
         7 . The device of  claim 1 , wherein the device is configured to operate as a field effect transistor. 
     
     
         8 . The device of  claim 1 , wherein the field-controlling element is at least partially isolated from the semiconductor by an isolation layer having a sheet resistance at least an order of magnitude higher than a sheet resistance of the field-controlling element. 
     
     
         9 . The device of  claim 1 , further comprising a connector for applying at least one of: an external bias or an external signal to the field-controlling element. 
     
     
         10 . The device of  claim 1 , wherein the field-controlling element forms a field-modulating plate for the at least one of the set of contacts. 
     
     
         11 . The device of  claim 1 , wherein the field-controlling element forms at least one of: a passivation layer or a strain relieving layer. 
     
     
         12 . The device of  claim 1 , wherein the semiconductor is formed of one of: silicon, silicon carbide, or a group III-V material. 
     
     
         13 . The device of  claim 1 , wherein the semiconductor is formed of a group III nitride material. 
     
     
         14 . A field-effect transistor comprising:
 a source contact, a drain contact, and a device channel there between;   a gate located on a first side of the device channel; and   a low conducting field-controlling element located on the first side of the device channel, wherein the field-controlling element is coupled to at least one of: the source contact, the drain contact, or the gate and wherein a lateral resistance of the field-controlling element is larger than an inverse of a minimal operating frequency of the device and the lateral resistance of the field-controlling element is smaller than an inverse of a maximum control frequency of the device.   
     
     
         15 . The transistor of  claim 14 , wherein the field-controlling element is a surface layer located between the gate and drain contact. 
     
     
         16 . The transistor of  claim 14 , wherein the field-controlling element is a surface layer located both between the source contact and the gate and between the gate and the drain contact. 
     
     
         17 . The transistor of  claim 14 , further comprising an insulating layer between the field-controlling element and the device channel, wherein the field-controlling element is attached to the gate and extends into an area between the gate and the drain. 
     
     
         18 . The transistor of  claim 14 , wherein the transistor includes a field-controlling plate for the gate and a field-controlling plate for at least one of: the source contact or the drain contact, and wherein at least one of the field-controlling plates is the field-controlling element. 
     
     
         19 . The transistor of  claim 14 , wherein the field-controlling element is capacitively coupled to the source contact, the transistor further comprising a second low conducting field-controlling element capacitively coupled to the drain contact. 
     
     
         20 . A method comprising:
 designing a semiconductor device including an active region, a set of contacts to the active region, and a field-controlling element located on a first side of the active region, wherein the designing includes:
 determining a target minimal operating frequency of the device and a target maximum control frequency of the device; 
 determining a target lateral resistance for the field-controlling element such that the target lateral resistance is both larger than an inverse of the target minimal operating frequency and smaller than an inverse of the target maximum control frequency; and 
 designing the field-controlling element based on the target lateral resistance.