Method, system, and device for l-shaped memory component

Abstract

Embodiments disclosed herein may relate to forming reduced size storage components in a cross-point memory array. In an embodiment, a storage cell comprising an L-shaped storage component having an approximately vertical portion extending from a first electrode positioned below the storage material to a second electrode positioned above and/or on the storage component. A storage cell may further comprise a selector material positioned above and/or on the second electrode and a third electrode positioned above and/or on the selector material, wherein the approximately vertical portion of the L-shaped storage component comprises a reduced size storage component in a first dimension.

1 . A method, comprising:
 forming a size of a first dimension and a second dimension of one or more storage components for a first trench and a second trench; the first trench positioned along a first direction in a dielectric material and the second trench positioned along a second direction in the dielectric material approximately orthogonal to the first direction; wherein the size of the first dimension is partially and/or substantially formed by deposition of storage component material over and/or on the dielectric material and the size of the second dimension is partially and/or substantially formed by a lithographic operation.   
     
     
         2 . The method of  claim 1 , wherein the depositing the storage component material comprises depositing phase change material over and/or on the dielectric material. 
     
     
         3 . The method of  claim 2 , wherein the phase change material comprises a chalcogenide glass material. 
     
     
         4 . The method of  claim 1 , wherein the depositing the storage component material over and/or on the dielectric material comprises depositing the storage component material over and/or on a nitride material. 
     
     
         5 . The method of  claim 1 , wherein the depositing the storage component material over and/or on the dielectric material comprises depositing the storage component material on one or more approximately vertical walls of one or more of the first and second trenches. 
     
     
         6 . The method of  claim 5 , wherein the one or more storage components comprise a memory array; and further comprising: depositing an additional dielectric material over and/or on the memory array, including filling the one or more of the first and second trenches. 
     
     
         7 . The method of  claim 6 , wherein the depositing the additional dielectric material over and/or on the memory array comprises depositing an oxide material over and/or on the memory array, including filling the one or more of the first and second trenches. 
     
     
         8 . The method of  claim 5 , further comprising planarizing a top surface of the memory array to remove a portion of the additional dielectric material and portions of the storage component material not located within the one or more of the first and second trenches, and to expose one or more top edges of approximately vertical portions of storage component material deposited on the one or more approximately vertical walls of the one or more trenches. 
     
     
         9 . The method of  claim 8 , further comprising:
 depositing an electrode material over and/or on the planarized surface of the memory array;   depositing a selector material over and/or on the electrode material; and   depositing an additional selector material over and/or on the selector material.   
     
     
         10 . The method of  claim 9 , further comprising etching one or more additional trenches positioned approximately along the first direction to at least partially isolate individual storage components of the memory array. 
     
     
         11 . The method of  claim 9 , wherein the etching the one or more additional trenches positioned approximately along the first direction comprises etching the one or more additional trenches positioned approximately along the first direction through the electrode material, the selector material, the additional electrode material, the dielectric material within the one or more trenches, and through a bottom electrode material. 
     
     
         12 . The method of  claim 11 , further comprising filling the memory array with additional dielectric material and planarizing the top surface of the memory array to expose the additional electrode material deposited on the selector material. 
     
     
         13 . The method of  claim 1 , wherein the forming the one or more additional trenches positioned approximately along the direction approximately orthogonal to the first direction in the one or more materials of the memory array comprises etching one or more sections of the one or more materials of the memory array utilizing a reduced pitch mask. 
     
     
         14 . A memory device, comprising:
 a storage cell comprising an L-shaped storage component having an approximately vertical portion extending from a first electrode positioned below the storage material to a second electrode positioned above and/or on the storage component, the storage cell further comprising a selector material positioned above and/or on the second electrode and a third electrode positioned above and/or on the selector material, wherein the approximately vertical portion of the L-shaped storage component comprises a reduced size storage component in a first dimension.   
     
     
         15 . The memory device of  claim 14 , wherein the storage cells comprises a phase change memory with selector (PCMS) storage cell. 
     
     
         16 . The memory device of  claim 15 , wherein the storage cell further comprises an integrated self-heating structure. 
     
     
         17 . The memory device of  claim 13 , wherein the reduced size of the storage component in the first dimension is partially and/or substantially affected by a deposition of storage component material on an approximately vertical wall of a trench located in a dielectric material. 
     
     
         18 . The memory device of  claim 17 , wherein the reduced size of the storage component in the first dimension is partially and/or substantially affected by a thickness of the storage component material deposition. 
     
     
         19 . The memory device of  claim 18 , wherein a size of the storage component in a second dimension is partially and/or substantially affected by an additional trench. 
     
     
         20 . The apparatus of  claim 19 , wherein the additional trench is positioned in a direction approximately orthogonal to the trench located in the dielectric material. 
     
     
         21 . A method, comprising:
 receiving one or more signals indicative of a memory access command from a processor of a computing platform; and   accessing a phase change memory with selector (PCMS) array of “L” shaped storage components in response to receiving the memory access command, wherein the accessing includes changing a state of one or more of the “L” shaped storage components of the PCMS array, wherein the one or more of the PCMS array of the “L” shaped storage components individually comprise an L-shaped storage material having an approximately vertical portion extending from a first electrode positioned below the storage component material to a second electrode positioned above and/or on the storage component material, the array of storage components further individually comprising a selector material positioned above and/or on the second electrode and a third electrode positioned above and/or on the selector material, wherein the approximately vertical portions of the L-shaped storage material of the individual storage components comprise a reduced size storage component in a first dimension.   
     
     
         22 . The method of  claim 21 , wherein the size of the storage component in the first dimension is partially and/or substantially affected by a deposition of storage component material to one or more approximately vertical walls of one or more trenches located in a dielectric material. 
     
     
         23 . The method of  claim 22 , wherein the size of the storage component in a second dimension is partially and/or substantially affected by one or more additional trenches formed in one or more materials of the array of storage components. 
     
     
         24 . The method of  claim 23 , wherein the one or more additional trenches are positioned along a direction approximately orthogonal to the one or more trenches located in the dielectric material.