US2013076424A1PendingUtilityA1

System and method for reducing cross coupling effects

46
Individually held — no corporate assignee on recordPriority: Sep 23, 2011Filed: Sep 23, 2011Published: Mar 28, 2013
Est. expirySep 23, 2031(~5.2 yrs left)· nominal 20-yr term from priority
Inventors:Baker MohammadPaul BassettMartin Saint-Laurent
G06F 3/00H03K 3/356113G06F 13/4077G06F 13/4291H03K 3/356069G06F 13/28G06F 13/4072H03K 5/15Y02D10/00
46
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Claims

Abstract

A device includes a plurality of driver circuits coupled to a plurality of bus lines. A first driver circuit of the plurality of driver circuits is coupled to a first bus line of the plurality of bus lines. The first driver circuit includes one of a skewed inverter, a level shifter, a latch, and a sense amplifier configured to produce an output signal that transitions after a first delay in response to a first digital value transition of an input signal from high to low and transitions after a second delay in response to a second digital value transition of the input signal from low to high. The first delay is different from the second delay by an amount sufficient to reduce power related to transmission of signals over the first bus line and over a second bus line in close physical proximity to the first bus line.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A device comprising:
 a plurality of driver circuits coupled to a plurality of bus lines, wherein a first driver circuit of the plurality of driver circuits is coupled to a first bus line of the plurality of bus lines and wherein the first driver circuit includes a delay element configured to produce an output signal that transitions after a first delay in response to a first digital value transition of an input signal from high to low and transitions after a second delay in response to a second digital value transition of the input signal from low to high, the first delay different from the second delay by an amount sufficient to reduce power related to transmission of signals over the first bus line and over a second bus line in close physical proximity to the first bus line,   wherein the delay element comprises a skewed inverter, a level shifter, a latch, or a sense amplifier.   
     
     
         2 . The device of  claim 1 , wherein the first driver circuit receives a clock signal and wherein the delay element is further configured to produce the output signal after detecting a transition in the clock signal. 
     
     
         3 . The device of  claim 1 , wherein the delay element comprises a skewed inverter. 
     
     
         4 . The device of  claim 3 , wherein the skewed inverter comprises:
 a first inverter that receives the input signal;   a second inverter that receives an output of the first inverter; and   a logic gate that receives the input signal and receives an output of the second inverter to produce the output signal.   
     
     
         5 . The device of  claim 4 , wherein the logic gate is a NAND gate or a NOR gate. 
     
     
         6 . The device of  claim 1 , wherein the amount is at least thirty picoseconds. 
     
     
         7 . The device of  claim 1 , wherein the amount is at least fifty picoseconds. 
     
     
         8 . The device of  claim 1 , wherein the amount is at least two logic gates delay. 
     
     
         9 . The device of  claim 1 , wherein the amount is at least three logic gates delay. 
     
     
         10 . The device of  claim 1 , wherein the delay element comprises a level shifter. 
     
     
         11 . The device of  claim 1 , wherein the delay element comprises a latch. 
     
     
         12 . The device of  claim 1 , wherein the delay element is a sense amplifier. 
     
     
         13 . A method comprising:
 receiving a first input signal at a delay element coupled to a first bus line of a plurality of bus lines, wherein the first input signal has a first digital value transition from high to low;   generating a first output signal at the delay element in response to the first input signal, wherein the first output signal transitions after a first delay;   receiving a second input signal at the delay element, wherein the second input signal has a second digital value transition from low to high; and   generating a second output signal at the delay element, wherein the second output signal transitions after a second delay, wherein the first delay is different from the second delay by an amount sufficient to reduce power related to transmission of signals over the first bus line and over a second bus line in close physical proximity to the first bus line, and   wherein the delay element comprises a skewed inverter, a level shifter, a latch, or a sense amplifier.   
     
     
         14 . The method of  claim 13 , further comprising:
 receiving a third input signal at a second delay element coupled to the second bus line concurrently with receiving the first input signal at the first delay element; and   generating a third output signal at the second delay element.   
     
     
         15 . The method of  claim 13 , wherein the amount is at least fifty picoseconds. 
     
     
         16 . The method of  claim 13 , wherein the amount is at least two logic gates delay. 
     
     
         17 . The method of  claim 13 , wherein the amount is at least three logic gates delay. 
     
     
         18 . An apparatus comprising:
 means for delaying an output signal at a first bus line of a plurality of bus lines based on a digital value transition of an input signal at the first bus line; and   wherein the output signal transitions after a first delay in response to a first digital value transition of the input signal from high to low and transitions after a second delay in response to a second digital value transition of the input signal from low to high, the first delay different from the second delay by an amount sufficient to reduce power related to transmission of signals over the first bus line and over a second bus line in close physical proximity to the first bus line,   wherein the means for delaying comprises a skewed inverter, a level shifter, a latch, or a sense amplifier.   
     
     
         19 . The apparatus of  claim 18 , further comprising means for providing the input signal to the means for delaying, wherein the means for providing comprises a component of an electronic device. 
     
     
         20 . The apparatus of  claim 18 , wherein the amount is at least fifty picoseconds or at least two logic gates delay.

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