Semiconductor system

Abstract

A semiconductor system includes a first clock channel and a second clock channel. The first clock channel transmits a first clock signal from a controller to a memory. The second clock channel transmits a second clock signal with a phase difference of 90° from the first clock signal, from the controller to the memory.

What is claimed is: 
     
         1 . A semiconductor system comprising:
 a first clock channel configured to transmit a first clock signal from a controller to a memory; and   a second clock channel configured to transmit a second clock signal with a phase difference of 90 degrees from the first clock signal, from the controller to the memory.   
     
     
         2 . The semiconductor system according to  claim 1 , wherein the second clock signal is generated by a phase-locked loop circuit that is included in the controller. 
     
     
         3 . The semiconductor system according to  claim 1 , wherein the first and second clock signals have the same frequency. 
     
     
         4 . The semiconductor system according to  claim 1 , further comprising:
 a third clock channel configured to transmit a third clock signal with a phase difference of 180 degrees from the first clock signal, from the controller to the memory.   
     
     
         5 . The semiconductor system according to  claim 4 , further comprising:
 a fourth clock channel configured to transmit a fourth clock signal with a phase difference of 180 degrees from the second clock signal, from the controller to the memory.   
     
     
         6 . A semiconductor system comprising:
 a first clock channel configured to transmit a first clock signal from a controller to a memory;   a second clock channel configured to transmit a second clock signal with the same frequency as the first clock signal, from the controller to the memory; and   a third clock channel configured to transmit a third clock signal with the same frequency as the second clock signal and a different phase from the second clock signal, from the controller to the memory.   
     
     
         7 . The semiconductor system according to  claim 6 , wherein the first and second clock signals have the same phase. 
     
     
         8 . The semiconductor system according to  claim 6 , wherein the third clock signal has a phase difference of 90 degrees from the second clock signal. 
     
     
         9 . The semiconductor system according to  claim 6 , wherein the first through third clock signals are generated by a phase-locked loop circuit that is included in the controller. 
     
     
         10 . The semiconductor system according to  claim 6 , further comprising:
 a fourth clock channel configured to transmit a fourth clock signal with a phase difference of 180 degrees from the first clock signal, from the controller to the memory.   
     
     
         11 . The semiconductor system according to  claim 6 , further comprising:
 a fifth clock channel configured to transmit a fifth clock signal with a phase difference of 180 degrees from the second clock signal, from the controller to the memory.   
     
     
         12 . The semiconductor system according to  claim 11 , further comprising:
 a sixth clock channel configured to transmit a sixth clock signal with a phase difference of 180 degrees from the third clock signal, from the controller to the memory.   
     
     
         13 . The semiconductor system according to  claim 6 , wherein the memory uses the second and third clock signals for data input/output operations and uses the first clock signal for operations other than the data input/output operations. 
     
     
         14 . A semiconductor system comprising:
 a controller configured to output a first clock signal and a second clock signal with a phase difference of 90 degrees from the first clock signal, in a normal mode; and   a memory configured to operate in response to the first and second clock signals.   
     
     
         15 . The semiconductor system according to  claim 14 , wherein the controller includes a phase-locked loop circuit which generates the first and second clock signals. 
     
     
         16 . The semiconductor system according to  claim 14 , wherein the controller outputs the first clock signal and does not output the second clock signal in a power-down mode. 
     
     
         17 . The semiconductor system according to  claim 14 , wherein the controller further outputs a third clock signal with a phase difference of 180 degrees from the first clock signal and a fourth clock signal with a phase difference of 180 degrees from the second clock signal. 
     
     
         18 . A semiconductor system comprising:
 a controller configured to output a first clock signal, a second clock signal with the same frequency as the first clock signal, and a third clock signal with the same frequency as the second clock signal and a different phase from the second clock signal, in a normal mode; and   a memory configured to operate in response to the first through third clock signals.   
     
     
         19 . The semiconductor system according to  claim 18 , wherein the first clock signal and the second clock signal have the same phase. 
     
     
         20 . The semiconductor system according to  claim 18 , wherein the third clock signal has a phase difference of 90 degrees from the second clock signal. 
     
     
         21 . The semiconductor system according to  claim 18 , wherein the controller includes a phase-locked loop circuit that generates the first through third clock signals. 
     
     
         22 . The semiconductor system according to  claim 18 , wherein the controller configured to output the first clock signal and does not output the second and third clock signals in a power-down mode. 
     
     
         23 . The semiconductor system according to  claim 18 , wherein the controller further outputs a fourth clock signal with a phase difference of 180 degrees from the first clock signal, a fifth clock signal with a phase difference of 180 degrees from the second clock signal, and a sixth clock signal with a phase difference of 180 degrees from the third clock signal. 
     
     
         24 . The semiconductor system according to  claim 18 , wherein the memory configured to perform data input/output operations in response to the second and third clock signals, and uses the first clock signal when performing operations excluding the data input/output operations. 
     
     
         25 . The semiconductor system according to  claim 18 , wherein the memory configured to receive the first through third clock signals and generates a first internal clock signal, a second internal clock signal, a third internal clock signal, and a fourth internal clock signal. 
     
     
         26 . The semiconductor system according to  claim 19 , wherein the first through fourth internal clock signals are immediately generated by receiving the first through third clock signals from the controller.