Charge trap type non-volatile memory device and method for fabricating the same

Abstract

There is provided a charge trap type non-volatile memory device and a method for fabricating the same, the charge trap type non-volatile memory device including: a tunnel insulation layer formed over a substrate; a charge trap layer formed over the tunnel insulation layer, the charge trap layer including a charge trap polysilicon thin layer and a charge trap nitride-based layer; a charge barrier layer formed over the charge trap layer; a gate electrode formed over the charge barrier layer; and an oxide-based spacer formed over sidewalls of the charge trap layer and provided to isolate the charge trap layer.

What is claimed is: 
     
         1 . A method of fabricating a charge trap type non-volatile memory device, comprising:
 forming a tunnel insulation layer over a substrate;   forming a charge trap layer over the tunnel insulation layer, the charge trap layer including a charge trap polysilicon thin layer and a charge trap nitride-based layer;   forming a charge barrier layer over the charge trap layer;   forming a gate electrode conductive layer over the charge barrier layer;   etching the gate electrode conductive layer, the charge barrier layer, the charge trap layer, and the tunnel insulation layer to form a charge trap structure; and   forming an oxide-based spacer over sidewalls of the etched charge trap layer, wherein forming the charge trap structure comprises:   etching the gate electrode conductive layer to form a gate electrode;   forming a nitride-based spacer over sidewalls of the gate electrode;   etching the charge barrier layer, the charge trap layer, and the tunnel insulation layer using the nitride-based spacer, wherein the tunnel insulation layer is partially etched so that the substrate is not exposed; and   performing an oxidation process over the substrate structure to form an oxide-based spacer over sidewalls of the etched charge trap layer.   
     
     
         2 . The method of  claim 1 , wherein the performing the oxidation process comprises using a radical oxidation method. 
     
     
         3 . The method of  claim 1 , wherein forming the charge trap polysilicon thin layer comprises:
 forming an amorphous silicon layer over the tunnel insulation layer;   crystallizing and oxidizing the amorphous silicon layer using an oxidation process; and   removing an oxide-based layer formed after performing the oxidation process to form the charge trap polysilicon thin layer having a uniform thickness.   
     
     
         4 . The method of  claim 3 , wherein the oxidizing the amorphous silicon layer comprises performing one of a wet oxidation method, a dry oxidation method, and a radical oxidation method. 
     
     
         5 . The method of  claim 1 , wherein forming the charge trap nitride-based layer comprises:
 forming a first nitride-based layer over the charge trap polysilicon thin layer; and   forming a second nitride-based layer over the first nitride-based layer, the second nitride-based layer having a higher nitrogen content than the first nitride-based layer.