Dual PCI-X/PCI-E Card

Abstract

A dual bus interface PCB includes a main chipset component, a first type bus interface connector, and a second type bus interface connector. The PCB can be configured at fabrication time to enable a variety of configurations for operation. Optionally, the PCB can also be provided at least one memory chip and a NIC (Network Interface Card) chip. By virtue of having a dual interface, the PCB can be used with either the first type or the second type bus. Furthermore, the dual interface PCB eliminates the need by chipset manufacturers to carry multiple PCB variations of the same product in order to support various bus interfaces. In one embodiment, the PCB is a dual PCI-X/PCI-E interface PCB.

1 . A circuit board assembly, comprising:
 a circuit board;   a first bus interface connector mounted to the circuit board, the first bus interface connector configured for a first interface protocol;   a second bus interface connector mounted to the circuit board, the second bus interface configured for a second interface protocol;   an integrated circuit chip mounted to the circuit board and configured to interface with at least one of the first and second bus interface connectors;   a first connector port selectively coupled to the integrated circuit chip when the first bus interface connector is enabled; and   a second connector port selectively coupled to the integrated circuit chip when the second bus interface connector is enabled.   
     
     
         2 . The circuit board assembly of  claim 1 , wherein the circuit board is insertable into a motherboard by selectively inserting either the first or the second interface connector into a corresponding slot of the motherboard. 
     
     
         3 . The circuit board assembly of  claim 1 , wherein the integrated circuit chip is mounted to a first surface of the circuit board, and wherein the first and second connector ports are mounted onto a second surface of the circuit board. 
     
     
         4 . The circuit hoard assembly of  claim 3 , wherein the first and second connector ports are mounted in a central region of the second surface of the circuit board. 
     
     
         5 . The circuit board assembly of  claim 1 , further comprising:
 a first set of signal traces routed from the integrated circuit chip to the first bus interface connector; and   a second set of signal traces routed from the integrated circuit chip to the second bus interface connector.   
     
     
         6 . The circuit board assembly of  claim 1 , wherein the first bus interface connector comprises a Peripheral Component Interconnect-Extended (PCI-X) bus interface connector, and the second bus interface connector comprises a Peripheral Component Interconnect-Express (PCI-X) bus interface connector. 
     
     
         7 . The circuit board assembly of  claim 1 , wherein the first and second connector ports comprise SATA/SAS connector ports. 
     
     
         8 . The circuit board assembly of  claim 1 , further comprising:
 a memory chip mounted to the circuit board and coupled to the integrated circuit chip.   
     
     
         9 . The circuit board assembly of  claim 1 , wherein the integrated circuit chip comprises a RAID controller. 
     
     
         10 . The circuit board assembly of  claim 9 , wherein the first and second connector ports connect the RAID controller to an array of disk drives. 
     
     
         11 . The circuit board assembly of  claim 1 , wherein the first bus interface connector and the second bus interface connector are mounted on opposite edges of the circuit board. 
     
     
         12 . The circuit board assembly of  claim 1 , further comprising:
 a Network Interface Card (NIC) chip mounted to the circuit board and coupled to the integrated circuit; and   an Ethernet connected mounted to the circuit board and coupled to the NIC chip.   
     
     
         13 . The circuit board assembly of  claim 1 , wherein the first bus interface connector and the second bus interface connector are both enabled. 
     
     
         14 . A circuit board assembly, comprising:
 a circuit board;   a first bus interface connector mounted to the circuit board, the first bus interface connector configured for a first interface protocol;   a second bus interface connector mounted to the circuit board, the second bus interface configured for a second interface protocol;   a first connector port mounted to the circuit board, the first connector port enabled when the first interface protocol is used by the circuit board assembly; and   a second connector port mounted to the circuit board, the second connector port enabled when the second interface protocol is used by the circuit board assembly.   
     
     
         15 . The circuit board assembly of  claim 14 , further comprising:
 an integrated circuit chip mounted to the circuit board and configured to interface with at least one of the first and second bus interface connectors.   
     
     
         16 . The circuit board assembly of  claim 15 , wherein the first connector port is coupled to the integrated circuit chip when the first interface protocol is used by the circuit board assembly, and wherein the second connector port is coupled to the integrated circuit when the second interface protocol is used by the circuit board assembly. 
     
     
         17 . The circuit board assembly of  claim 14 , wherein the first bus interface connector comprises a Peripheral Component Interconnect-Extended (PCI-X) bus interface connector, and the second bus interface connector comprises a Peripheral Component Interconnect-Express (PCI-E) bus interface connector. 
     
     
         18 . A method of making a dual bus interface circuit board, comprising:
 mounting a first bus interface connector and a second bus interface connector onto opposite edges of a circuit board;   mounting an integrated circuit chip on the circuit board;   routing a first set of signal traces and a second set of signal traces from the integrated circuit chip to the first and second bus interface connectors, respectively;   coupling a first connector port to the integrated circuit chip when the first bus interface connector is enabled; and   coupling a second connector port to the integrated circuit chip when the second bus interface connector is enabled.   
     
     
         19 . The method of  claim 18 , further comprising:
 selectively mounting resistors at first ends of at least one of the first and the second sets of signal traces to selectively enable at least one of the first and second bus interface connectors.   
     
     
         20 . The method of  claim 18 , wherein the first bus interface connector comprises a Peripheral Component Interconnect-Extended (PCI-X) bus interface connector, and the second bus interface connector comprises a Peripheral Component Interconnect-Express (PCI-E) bus interface connector.