Semiconductor device and method for manufacturing same

Abstract

A terrace insulating film (SL) to be overridden by a gate electrode (G) of an nLDMOS device is configured by LOCOS, and a device isolation portion (SS) is configured by STI. Furthermore, on an outermost periphery of an active region where a plurality of nLDMOS devices are formed, a guard ring having the same potential as that of a drain region (D) is provided. And, via this guard ring, the device isolation portion (SS) is formed in a periphery of the active region, thereby not connecting but isolating the terrace insulating film (SL) and the device isolation portion (SS) from each other.

1 .- 44 . (canceled) 
     
     
         45 . A semiconductor device comprising, in an active region surrounded by a device isolation portion formed on a main surface of a semiconductor layer on a substrate, a field-effect transistor including:
 a source region formed along a first direction;   a terrace insulating film formed in a periphery of the source region with a predetermined distance away from the source region;   a drain region formed along the first direction on both sides of the source region in a second direction that is orthogonal to the first direction via the terrace insulating film; and   a gate electrode formed on the main surface of the semiconductor layer between the source region and the drain region via a gate insulating film so as to partially override the terrace insulating film,   wherein, in an outermost periphery of the active region, a semiconductor region is formed on the semiconductor layer between the terrace insulating film and the device isolation portion in the first direction and between the terrace insulating film and the device isolation portion in the second direction,   wherein the device isolation portion and the terrace insulating film are isolated from each other,   wherein the terrace insulating film is formed by LOCOS, and   wherein the device isolation portion is formed by STI which includes an insulating film embedded in a groove formed in the semiconductor layer.   
     
     
         46 . The semiconductor device according to  claim 45 ,
 wherein the terrace insulating film has a thickness smaller than a thickness of the device isolation portion.   
     
     
         47 . The semiconductor device according to  claim 45 ,
 wherein the terrace insulating film has a thickness smaller than or equal to 200 nm.   
     
     
         48 . The semiconductor device according to  claim 45 ,
 wherein a distance between a center part of the source region and a center part of the drain region is shorter than 6 μm.   
     
     
         49 . The semiconductor device according to  claim 45 ,
 wherein an upper surface of the LOCOS does not fall from the main surface of the semiconductor layer.   
     
     
         50 . The semiconductor device according to  claim 45 ,
 wherein the semiconductor region formed between the terrace insulating film and the device isolation portion functions as a guard ring.   
     
     
         51 . The semiconductor device according to  claim 45 ,
 wherein the semiconductor region formed at ends in the first direction of the drain region or the source region is connected.   
     
     
         52 . The semiconductor device according to  claim 45 ,
 wherein the first direction is a channel width direction, and the second direction is a channel length direction.   
     
     
         53 . The semiconductor device according to  claim 45 ,
 wherein the terrace insulating film formed in the periphery of the source region has a planar shape of a rectangular frame, a rectangular frame having its four angles tilted by 45 degrees, or a rectangular frame having its four corners rounded.   
     
     
         54 . A semiconductor device comprising, in an active region surrounded by a device isolation portion formed on a main surface of a semiconductor layer of a first conductive type on a substrate, a field-effect transistor including:
 a drain region of a second conductive type that is different from the first conductive type, the drain region being formed along a first direction;   a first terrace insulating film formed adjacent to the drain region;   a source region of the second conductive type formed along the first direction at both sides of the drain region in a second direction that is orthogonal to the first direction with a predetermined distance away from the first terrace insulating film;   a gate electrode formed on the main surface of the semiconductor layer between the drain region and the source region via a gate insulating film so as to partially override the terrace insulating film;   a second terrace insulating film formed in a periphery of the drain region and the source region and connecting to the first terrace insulating film; and   a semiconductor region of the first conductive type formed in a periphery of the second terrace insulating film,   wherein the device isolation portion and the second terrace insulating film are isolated from each other,   wherein the terrace insulating film is formed by LOCOS, and   wherein the device isolation portion is formed by STI which includes an insulating film embedded in a groove formed in the semiconductor layer.   
     
     
         55 . The semiconductor device according to  claim 54 ,
 wherein the first and second terrace insulating films have thicknesses smaller than a thickness of the device isolation portion.   
     
     
         56 . The semiconductor device according to  claim 54 ,
 wherein the first and second terrace insulating films have thicknesses each smaller than or equal to 200 nm.   
     
     
         57 . The semiconductor device according to  claim 54 ,
 wherein the semiconductor region formed between the second terrace insulating film and the device isolation portion functions as a power feeding part.   
     
     
         58 . A semiconductor device comprising, in an active region surrounded by a device isolation portion formed on a main surface of a semiconductor layer of a first conductive type on a substrate, a diode including:
 an anode region formed in a center part of the active region; and   a cathode region formed in a periphery of the anode region via a terrace insulating film,   wherein the anode region is configured of a silicide film formed on a surface of the semiconductor layer and a first semiconductor region of a second conductive type that is different from the first conductive type formed on the semiconductor layer in a periphery of the silicide   wherein the cathode region is configured of a second semiconductor region of the first conductive type formed on the semiconductor layer,   wherein the terrace insulating film is formed on a joint surface between the first semiconductor region of the anode region and the second semiconductor region of the cathode region,   wherein the terrace insulating film is formed by LOCOS, and   wherein the device isolation portion is formed by STI which includes an insulating film embedded in a groove formed in the semiconductor layer.   
     
     
         59 . The semiconductor device according to  claim 58 ,
 wherein the device isolation portion and the terrace insulating film are isolated from each other.   
     
     
         60 . The semiconductor device according to  claim 58 ,
 wherein the terrace insulating film has a thickness smaller than a thickness of the device isolation portion.   
     
     
         61 . The semiconductor device according to  claim 58 ,
 wherein the terrace insulating film has a thickness smaller than or equal to 200 nm.   
     
     
         62 . The semiconductor device according to  claim 58 ,
 wherein the terrace insulating film has a planar shape of a ring.   
     
     
         63 . The semiconductor device according to  claim 58 ,
 wherein a gate electrode short-circuited with the anode region is formed on the terrace insulating film.   
     
     
         64 . The semiconductor device according to  claim 58 ,
 wherein the second semiconductor region is formed of a first region having a first impurity concentration, a second region having a second impurity concentration lower than the first impurity concentration, the second region being formed so as to surround the first region, and a third region having a third impurity concentration lower than the second impurity concentration, the third region being formed so as to surround the second region.   
     
     
         65 . A semiconductor device comprising, in an active region surrounded by a device isolation portion formed on a main surface of a semiconductor layer of a first conductive type on a substrate, a capacitative element including:
 a first electrode formed of a first semiconductor region of a second conductive type different from the first conductive type on the semiconductor layer of the active region;   a capacitance insulating film formed of a terrace insulating film formed on the main surface of the semiconductor layer in a center part of the active region where the first semiconductor region is formed; and   a second electrode formed of a conductive film formed on the terrace insulating film,   wherein the first semiconductor region is formed between the terrace insulating film and the device isolation portion in a planar view,   wherein the terrace insulating film is formed by LOCOS, and   wherein the device isolation portion is formed by STI which includes an insulating film embedded in a groove formed in the semiconductor layer.   
     
     
         66 . The semiconductor device according to  claim 65 ,
 wherein the device isolation portion and the terrace insulating film are isolated from each other.   
     
     
         67 . The semiconductor device according to  claim 65 ,
 wherein the terrace insulating film has a thickness smaller than a thickness of the device isolation portion.   
     
     
         68 . A semiconductor device comprising, in an active region surrounded by a device isolation portion formed on a main surface of a semiconductor layer of a first conductive type on a substrate, a capacitative element including:
 a capacitance insulating film formed of a first insulating film formed on the main surface of the semiconductor layer of the active region;   a first electrode formed of a first semiconductor region of the first conductive type formed on the semiconductor layer under the first insulating film; and   a second electrode formed of a conductive film formed on the first insulating film,   wherein a second semiconductor region of a second conductive type that is different from the first conductive type is formed in a periphery of the first semiconductor region, and   wherein the second semiconductor region is formed between the terrace insulating film and the device isolation portion in a planar view.   
     
     
         69 . The semiconductor device according to  claim 68 ,
 wherein the device isolation portion and the terrace insulating film are isolated from each other.   
     
     
         70 . The semiconductor device according to  claim 68 ,
 wherein the terrace insulating film has a thickness smaller than a thickness of the device isolation portion and is thicker than a thickness of the first insulating film.   
     
     
         71 . The semiconductor device according to  claim 68 ,
 wherein the second electrode partially overrides the terrace insulating film.   
     
     
         72 . A semiconductor device comprising, in an active region surrounded by a device isolation portion formed on a main surface of a semiconductor layer of a first conductive type on a substrate, a bipolar-type protective element including:
 an emitter formed of a first semiconductor region of the first conductive type formed on the semiconductor layer in a center part of the active region;   a base formed of a second semiconductor region of a second conductive type different from the first conductive type in a periphery of the first semiconductor region;   a terrace insulating film formed on the main surface of the semiconductor layer in a periphery of the second semiconductor region; and   a collector formed of a third semiconductor region of the first conductive type formed in a periphery of the terrace insulating film,   wherein the third semiconductor region is formed between the terrace insulating film and the device isolation portion in a planar view,   wherein the terrace insulating film is formed by LOCOS, and   wherein the device isolation portion is formed by STI which includes an insulating film embedded in a groove formed in the semiconductor layer.   
     
     
         73 . The semiconductor device according to  claim 72 ,
 wherein the device isolation portion and the terrace insulating film are isolated from each other.   
     
     
         74 . The semiconductor device according to  claim 72 ,
 wherein the terrace insulating film has a thickness smaller than a thickness of the device isolation portion.   
     
     
         75 . The semiconductor device according to  claim 72 ,
 wherein a gate electrode is formed on the terrace insulating film to short-circuit the first semiconductor region, the second semiconductor region, and the gate electrode.   
     
     
         76 . The semiconductor device according to  claim 72 ,
 wherein a buried layer of the first conductive type having a concentration higher than a concentration of the semiconductor layer is formed under the semiconductor layer, and a fourth semiconductor region having a concentration higher than the concentration of the semiconductor layer and lower than the concentration of the buried layer is formed between the second semiconductor region and the buried layer and between the third semiconductor region and the buried layer.   
     
     
         77 . A method of manufacturing a semiconductor device comprising the steps of
 (a) forming a device isolation portion that surrounds an active region of a semiconductor layer of a first conductive type formed on a substrate, the device isolation portion being formed on a main surface of the semiconductor layer;   (b) forming a terrace insulating film having a predetermined width on the main surface of the semiconductor layer in the active region surrounded by the device isolation portion, the terrace insulating film being formed with a predetermined distance away from the device isolation portion; and   (c) forming a well of the first conductive type on the semiconductor layer between the device isolation portion and the terrace insulating film, the step (a) further including the steps of:   (a1) forming a groove in the semiconductor layer;   (a2) depositing an insulating film on the main surface of the semiconductor layer; and   (a3) forming the device isolation portion formed of the insulating film embedded inside the groove by polishing the insulating film to leave the insulating film only inside the groove, and   the step (b) further including the steps of:   (b1) forming a first insulating film on the main surface of the semiconductor layer and forming a second insulating film on the first insulating film;   (b2) sequentially removing the second insulating film and the first insulating film each having a predetermined width with a predetermined distance away from the device isolation portion; and   (b3) forming the terrace insulating film on the main surface of the semiconductor layer with the second insulating film and the first insulating film removed by performing a thermal oxidation process on the semiconductor layer.   
     
     
         78 . The method of manufacturing a semiconductor device according to  claim 77 ,
 wherein the device isolation portion and the terrace insulating film are isolated from each other.   
     
     
         79 . The method of manufacturing a semiconductor device according to  claim 77 ,
 wherein the terrace insulating film has a thickness smaller than a thickness of the device isolation portion.   
     
     
         80 . A method of manufacturing a semiconductor device having a field-effect transistor of a lateral structure, the method comprising the steps of:
 (a) forming a device isolation portion that surrounds an active region of a semiconductor layer of a first conductive type formed on a substrate, the device isolation portion being formed on a main surface of the semiconductor layer;   (b) forming a terrace insulating film having a predetermined width on the main surface of the semiconductor layer in the active region surrounded by the device isolation portion, the terrace insulating film being formed with a predetermined distance away from the device isolation portion;   (c) forming a first well of a second conductive type that is different from the first conductive type in the active region surrounded by the terrace insulating film, the first well serving as a channel region;   (d) forming a second well of the first conductive type on the semiconductor layer between the device isolation portion and the terrace insulating film;   (e) forming a gate insulating film on the main surface of the semiconductor layer;   (f) forming a gate electrode on the gate insulating film, with one end in a gate length direction overriding the terrace insulating film and another end partially covering a region where the first well is formed;   (g) forming sidewalls on side walls of the gate electrode;   (h) forming a first semiconductor region of the first conductive type on the first well outside the sidewall formed on a side surface of one end of the gate electrode; and   (i) forming a second semiconductor region of the first conductive type on the second well between the device isolation portion and the terrace insulating film,   the step (a) further including the steps of:   (a1) forming a groove in the main surface of the semiconductor layer;   (a2) depositing an insulating film on the main surface of the semiconductor layer; and   (a3) forming the device isolation portion formed of the insulating film embedded inside the groove by polishing the insulating film to leave the insulating film only inside the groove, and   the step (b) further including the steps of:   (b1) forming a first insulating film on the main surface of the semiconductor layer and forming a second insulating film on the first insulating film;   (b2) sequentially removing the second insulating film and the first insulating film each having a predetermined width and a predetermined distance away from the device isolation portion; and   (b3) forming the terrace insulating film on the main surface of the semiconductor layer with the second insulating film and the first insulating film removed by performing a thermal oxidation process on the semiconductor layer.   
     
     
         81 . The method of manufacturing a semiconductor device according to  claim 80 ,
 wherein the device isolation portion and the terrace insulating film are isolated from each other.   
     
     
         82 . The method of manufacturing a semiconductor device according to claim  480   wherein the terrace insulating film has a thickness smaller than a thickness of the device isolation portion.