Low-Power Modulation in an Amplifier

Abstract

A switching audio amplifier may include a modulation enhancement feature, in which the pulse-width modulated (PWM) signals driving the output stage are reduced or increased by identical step sizes to create an auxiliary PWM scheme representative of an idle (low-power) state of the input signal. The PWM signals, provided to a full-bridge power stage circuit for example, may be thereby reduced to another state to reduce power dissipation in a switch-mode power supply. By incrementally adjusting the PWM duty-cycle identically in all PWM signals to a value less than (or up to) 50%, the amount of current dissipated in the output load may be effectively controlled. The PWM pulses may be adjusted up or down, while checking for saturation corresponding to both minimum and maximum pulse-widths. A dampener circuit may be used to set the time between incremental adjustments, to further reduce audible pops and clicks.

1 . A signal processing system comprising:
 a signal processing circuit configured to receive an input signal, and generate a first control value representative of the input signal;   an auxiliary circuit configured to generate a second control value representative of an idle state of the input signal;   a control circuit configured to receive an input control value and generate a control signal representative of the input signal according to the received input control value; and   a selection circuit configured to select and provide:
 the first control value as the input control value to the control circuit, responsive to an indication that the input signal is not in the idle state; and 
 the second control value as the input control value to the control circuit, responsive to an indication that the input signal is in the idle state. 
   
     
     
         2 . The signal processing system of  claim 1 , wherein the first control value, the second control value, and the input control value represent duty-cycle values, and wherein the control signal is a pulse-width modulated (PWM) signal having a duty-cycle defined by the input control value. 
     
     
         3 . The signal processing system of  claim 1 , further comprising:
 an indicator circuit configured to generate an event signal indicative of whether or not the input signal is in the idle state.   
     
     
         4 . The signal processing system of  claim 3 , wherein the indicator circuit is configured to assert the event signal to indicate that the input signal has entered the idle state, in response to one or more of:
 a button being pushed; or   the input signal falling below a specified level.   
     
     
         5 . The signal processing system of  claim 1 , wherein the auxiliary circuit is configured to perform one or more of:
 gradually decrease the second control value over a time period of specified length until the second control value reaches a minimum value, responsive to an event indicating that the input signal has entered the idle state; or   gradually increase the second control value over a time period of specified length until the second control value reaches a default value, responsive to an event indicating that the input signal has exited the idle state.   
     
     
         6 . The signal processing system of  claim 5 , wherein the auxiliary circuit is further configured to perform one or more of:
 hold the second control value at the default value for a time period of specified length before gradually decreasing the second control value; or   hold the second control value at the minimum value for a time period of specified length before gradually increasing the second control value.   
     
     
         7 . The signal processing system of  claim 6 , wherein the specified length of each time period is programmable. 
     
     
         8 . The signal processing system of  claim 6 , wherein the first control value, the second control value, and the input control value represent duty-cycle values, and wherein the control signal is a pulse-width modulated (PWM) signal having a duty-cycle defined by the input control value;
 wherein the default value represents a 50% duty-cycle value.   
     
     
         9 . The signal processing system of  claim 1 , wherein the signal processing system is an amplifier, wherein the input signal is an audio signal, and wherein the output signal is an amplified version of the audio signal. 
     
     
         10 . A method for generating an output signal without transients, the method comprising:
 receiving an input signal, and generating a first control value representative of the input signal;   generating a second control value representative of an idle state of the input signal;   receiving in a control circuit an input control value, and generating a control signal representative of the input signal according to the received control value;   receiving an indication of whether or not the input signal is in the idle state;   selecting and providing the first control value as the input control value to the control circuit, if the indication is of the input signal not being in the idle state; and   providing the second control value as the input control value to the control circuit, if the indication is of the input signal being in the idle state.   
     
     
         11 . The method of  claim 10 , wherein the first control value, the second control value, and the input control value are duty-cycle values, and wherein the control signal is a pulse-width modulated (PWM) signal having a duty-cycle represented by the input control value. 
     
     
         12 . The method of  claim 11 , further comprising:
 generating an output signal according to the control signal, wherein the output signal corresponds to the input signal.   
     
     
         13 . The method of  claim 12 , wherein the input signal is an audio signal and the output signal is an amplified version of the input signal. 
     
     
         14 . The method of  claim 10 , further comprising:
 generating an event signal as the indication of whether or not the input signal is in the idle state.   
     
     
         15 . The method of  claim 14 , wherein said generating the event signal comprises asserting the event signal to provide the indication that the input signal has entered the idle state, responsive to one or more of:
 a button being pushed; or   the input signal falling below a specified level.   
     
     
         16 . The method of  claim 10 , further comprising one or more of:
 gradually decreasing the second control value over a first time period of specified length until the second control value reaches a minimum value, responsive to an event indicating that the input signal has just entered the idle state; or   gradually increasing the second control value over a second time period of specified length until the second control value reaches a default value, responsive to an event indicating that the input signal has just exited the idle state.   
     
     
         17 . The method of  claim 16 , further comprising one or more of:
 holding the second control value at the default value for a third time period of specified length subsequent to the event indicating that the input signal has just entered the idle state, prior to said gradually decreasing the second control value; or   holding the second control value at the minimum value for a fourth time period of specified length subsequent to the event indicating that the input signal has just exited the idle state, prior to said gradually increasing the second control value.   
     
     
         18 . The method of  claim 17 , further comprising programming the specified length of each time period prior to:
 said gradually decreasing the second control value;   said gradually increasing the second control value;   said holding the second control value at the default value; and   said holding the second control value at the minimum value.   
     
     
         19 . The method of  claim 17 , wherein the first control value, the second control value, and the input control value represent duty-cycle values, and wherein the control signal is a pulse-width modulated (PWM) signal having a duty-cycle represented by the input control value;
 wherein the default value represents a 50% duty-cycle value.   
     
     
         20 . The method of  claim 16 , wherein said gradually decreasing the second control value comprises decreasing the second control value by a specified decrement value a specified number of times within the first time period. 
     
     
         21 . The method of  claim 16 , wherein said gradually increasing the second control value comprises increasing the second control value by a specified increment value a specified number of times within the second time period. 
     
     
         22 . A circuit for modifying an output signal representative of an input signal when the input signal is in an idle state, the circuit comprising:
 a selection circuit configured to:
 receive a first control value representative of a present value of the input signal, and a second control value representative of the input signal being in the idle state; 
 provide the first control value as an input control value to a control circuit, responsive to an indication that the input signal is not in an idle state, wherein the control circuit is configured to generate a control signal representative of the input signal according to the input control value; and 
 provide the second control value as the input control value to the control circuit, responsive to an indication that the input signal is in the idle state; and 
   an auxiliary circuit configured to incrementally adjust the second control value until the second control value reaches a desired value, responsive to one or more of:
 the input signal entering the idle state; or 
 the input signal exiting the idle state. 
   
     
     
         23 . The circuit of  claim 22 , wherein the idle state represents a low-power state. 
     
     
         24 . The circuit of  claim 22 , wherein the auxiliary circuit is configured to incrementally adjust the second control value at specified rate to reach the desired value within a time period of desired length. 
     
     
         25 . The circuit of  claim 24 , wherein in incrementally adjusting the second control value, the auxiliary circuit is configured to perform one or more of:
 incrementally increase the second control value from a minimum value to a default value, responsive to the input signal exiting the idle state; or   incrementally decrease the second control value from the default value to the minimum value, responsive to the input signal entering the idle state.   
     
     
         26 . The circuit of  claim 25 , wherein the first control value, the second control value, and the input control value represent duty-cycle values;
 wherein the control signal is a pulse-width modulated (PWM) signal having a duty-cycle defined by the input control value;   wherein the default value represents a 50% duty-cycle value.   
     
     
         27 . The circuit of  claim 25 , wherein the minimum value, the default value, and the desired length of the time period are programmable. 
     
     
         28 . The circuit of  claim 22 , further comprising:
 an indicator circuit configured to generate an event signal indicative of the input signal entering and exiting the idle state, and provide the event signal to the auxiliary circuit;   wherein the auxiliary circuit configured to incrementally adjust the second control value according to the event signal.   
     
     
         29 . The circuit of  claim 28 , wherein the indicator circuit is configured to assert the event signal to indicate that the input signal has entered the idle state, in response to one or more of:
 a button being pushed; or   the input signal falling below a specified level.   
     
     
         30 . The circuit of  claim 22 , wherein the auxiliary circuit is further configured to hold the second control value at its present value for a time period of specified length before starting to incrementally adjust the second control value, responsive to one or more of:
 the input signal entering the idle state; or   the input signal exiting the idle state.