Output Power Limiter in an Audio Amplifier

Abstract

An output power limiter system (PLS) for audio amplifiers may be designed as a feedback control system for protection of the load and/or quality of the audio experience. The PLS may use comparator to sense the output current, compare it to a specified threshold, and assert a signal when the output current reaches and exceeds the specified threshold. The output signal from the comparator may enable a counter that is clocked with a high frequency clock to begin counting to measure the pulse-width of the comparator output. The output of the counter may be averaged through a fast attack and slow release infinite impulse response (IIR) filter having programmable settings to generate a rate of attenuation or rate of release that adjusts a gain correction in terms of decibels (dB). The output of the IIR filter may then be used for attenuating the output current.

1 . A signal processing system comprising:
 signal processing circuitry configured to receive an input signal, generate a driver signal representative of the input signal, and use the driver signal to generate an output signal; and   power limiting circuitry configured to:   assert a first signal in response to an output current reaching a first threshold, wherein the output current is produced by the output signal;   derive a control value from the first signal, wherein the control value corresponds to a time duration for which the first signal is asserted;   attenuate the output signal by scaling the driver signal according to the control value.   
     
     
         2 . The signal processing system of  claim 1 , wherein the signal processing circuitry is an amplifier circuit, wherein the input signal is an audio signal, and wherein the output signal is an amplified version of the audio signal. 
     
     
         3 . The signal processing system of  claim 1 , further comprising a speaker coupled as a load to the signal processing circuitry, wherein the output current is conducted by the speaker. 
     
     
         4 . The signal processing system of  claim 1 , wherein the power limiting circuitry comprises:
 a comparator having an output configured to provide the first signal responsive to the comparator comparing the output current to the first threshold;   a digital circuit configured to generate a numeric value based on the first signal, wherein the numeric value corresponds to the time duration for which the first signal is asserted; and   a filter circuit configured to generate the control value from the numeric value.   
     
     
         5 . The signal processing system of  claim 4 , wherein the digital circuit is a counter that is clocked with a clock signal having a specified frequency higher than a frequency of the driver signal;
 wherein the counter is configured to:
 count when the first signal is asserted; 
 stop counting when the first signal is deasserted; and 
 provide a result of the count as the numeric value. 
   
     
     
         6 . The signal processing system of  claim 4 , wherein the filter circuit is an infinite impulse response (IIR) filter configured to average the numeric value, and provide the control value based on the averaged numeric value. 
     
     
         7 . The signal processing system of  claim 6 , wherein the IIR filter is a fast attack and slow release IIR filter. 
     
     
         8 . The signal processing system of  claim 7 , wherein the IIR filter comprises programmable settings for generating a rate of release. 
     
     
         9 . The signal processing system of  claim 1 , wherein the power limiting circuitry is further configured to:
 deassert the driver signal in response to the output current reaching a second threshold.   
     
     
         10 . The signal processing system of  claim 9 , wherein the second threshold is higher than the first threshold. 
     
     
         11 . The signal processing system of  claim 1 , wherein the driver signal is a pulse-width modulated (PWM) signal;
 wherein in scaling the driver signal according to the control value, the power limiting circuit is configured to adjust a pulse-width of the PWM signal.   
     
     
         12 . A power limiting circuit for limiting output power associated with an output current resulting from an output signal generated according to a driver signal, which is derived from an input signal, the power limiting circuit comprising:
 a comparator configured to assert a comparator output responsive to the output current exceeding a first threshold value; and   a scaler circuit configured to:
 derive a scaler value from the comparator output; and 
 attenuate the output signal by multiplying the scaler value with the input signal. 
   
     
     
         13 . The power limiting circuit of  claim 12 , wherein the scaler circuit is configured to generate the scaler value based on a time duration for which the comparator output is asserted. 
     
     
         14 . The power limiting circuit of  claim 12 , wherein the scaler comprises:
 a digital circuit configured to generate a numeric value corresponding to a time duration for which the comparator output is asserted; and   a filter circuit configured to generate the scaler value from the numeric value.   
     
     
         15 . The power limiting circuit of  claim 14 , wherein the digital circuit is a counter that is clocked with a clock signal having a specified frequency higher than a frequency of the driver signal;
 wherein the counter is configured to:
 count when the comparator output is asserted; 
 stop counting when the comparator output is deasserted; and 
 provide a result of the count as the numeric value. 
   
     
     
         16 . The power limiting circuit of  claim 14 , wherein the filter circuit is an infinite impulse response (IIR) filter configured to average the numeric value, and provide the scaler value based on the averaged numeric value. 
     
     
         17 . The power limiting circuit of  claim 16 , wherein the IIR filter is a fast attack and slow release IIR filter. 
     
     
         18 . The power limiting circuit of  claim 17 , wherein the IIR filter comprises programmable settings for generating a rate of release. 
     
     
         19 . The power limiting circuit of  claim 14 , further comprising:
 a second comparator configured to deassert the driver signal in response to the output current reaching a second threshold.   
     
     
         20 . The power limiting circuit of  claim 19 , wherein the second threshold is higher than the first threshold. 
     
     
         21 . A method for limiting output power in an audio amplifier, the method comprising:
 generating an output signal based on an input signal;   the output signal resulting in an output current;   asserting a control signal when the output current is over a specified first threshold;   generating a numeric value corresponding to a time duration for which the control signal is asserted;   averaging the numeric value;   scaling the averaged numeric value; and   attenuating the output signal by multiplying the scaled averaged numeric value with the input signal.   
     
     
         22 . The method of  claim 21 , wherein said generating the numeric value comprises:
 counting cycles of a clock signal while the control signal is asserted; and   providing a number of counted clock cycles as the numeric value.   
     
     
         23 . The method of  claim 21 , wherein said averaging the numeric value comprises filtering the numeric value using an infinite impulse response (IIR) filter. 
     
     
         24 . The method of  claim 21 , wherein said scaling the averaged numeric value comprises performing one of:
 a successive approximation register algorithm using the averaged numeric value as input; and   a linear reduction using the averaged numeric value as input.   
     
     
         25 . The method of  claim 21 , wherein said generating the output signal based on the input signal comprises:
 generating a pulse train representative of the input signal; and   generating the output signal by driving a power stage with the pulse train;   wherein the method further comprises adjusting the pulse train responsive to said multiplying the scaled averaged numeric value with the input signal.