Address Mapping in Memory Systems

Abstract

A memory system includes an address mapping circuit. The address mapping circuit receives an input memory address having a first set of address bits. The address mapping circuit applies a logic function to the input memory address to generate a mapped memory address. The logic function uses at least a subset of the first set of address bits in two separate operations that respectively determine two portions of the mapped memory address.

What is claimed is: 
     
         1 . A memory system comprising:
 an address mapping circuit to receive an input memory address comprising a first set of address bits, the address mapping circuit applying a logic function to the input memory address to generate a mapped memory address, the logic function using at least a subset of the first set of address bits in two separate operations that respectively determine first and second portions of the mapped memory address.   
     
     
         2 . The memory system of  claim 1 , further comprising:
 a dynamic wear leveling function to generate a wear-leveled memory address from at least one of the input memory address and the mapped memory address; and   a memory circuit to write data to a memory location in the memory circuit identified by the wear-leveled memory address.   
     
     
         3 . The memory system of  claim 1 , further comprising a wear leveling function operating in parallel with the address mapping circuit, the wear leveling function and the address mapping circuit generating respective portions of the mapped memory address. 
     
     
         4 . The memory system of  claim 1 , wherein the first set of address bits comprises first bits indicating a row address and second bits indicating a column address, wherein the logic function generates the mapped memory address with third bits indicating a row address and fourth bits indicating a column address, such that, for consecutive row addresses in an input memory address space, the third bits exhibit decreased row address locality as compared to the first bits, and for consecutive column addresses in the input memory address space, the fourth bits exhibit decreased column address locality as compared to the second bits. 
     
     
         5 . The memory system of  claim 1 , wherein the first set of address bits comprises first bits indicating a row address and second bits indicating a column address, wherein the logic function generates the mapped memory address with third bits indicating a row address and fourth bits indicating a column address, the logic function generating one or more of the third bits based at least in part on one or more of the second bits, and the logic function generating one or more of the fourth bits based at least in part on one or more of the first bits. 
     
     
         6 . The memory system of  claim 5 , wherein the logic function comprises an XOR function that generates a subset of the fourth bits as an XOR output of selected bits from the first and second bits. 
     
     
         7 . The memory system of  claim 5 , wherein the logic function comprises an offset function that applies a variable deterministic offset to at least a subset of the first and second bits to generate a subset of the fourth bits, the amount of the variable deterministic offset determined based on the value of an offset-determining bit subset of at least one of the first and second bits, and wherein the memory system further comprises an offset lookup table to hold a plurality of values for the variable deterministic offset, each value held in the lookup table indexed by a corresponding value of the offset-determining bit subset. 
     
     
         8 . The memory system of  claim 1 , wherein the logic function comprises an XOR function that generates the first portion of the mapped memory address as an XOR output of first and second subsets of selected bits from the first set of address bits. 
     
     
         9 . The memory system of  claim 1 , wherein the logic function comprises a circular arithmetic shift function of a partial address comprising a first portion of the first set of address bits, and wherein a value of the shift that the circular arithmetic shift function applies to the partial address is a function of a second portion of the first set of address bits. 
     
     
         10 . The memory system of  claim 1 , wherein the address mapping circuit comprises multiple logic functions providing different one-to-one mappings from the input memory address to the mapped memory address, and wherein the memory system further comprises a hot region guard mechanism to indicate to the address mapping circuit which of the multiple logic functions to apply to the input memory address to generate the mapped memory address. 
     
     
         11 . The memory system of  claim 10 , wherein the hot region guard mechanism tracks statistics representing a number of write requests and a number of unique regions written to based on the write requests, wherein the address mapping circuit is triggered to select, upon a next memory system restart, a different one of the multiple logic functions than the currently selected one of the multiple logic functions, in response to the statistics indicating low coverage by the write requests, and wherein the low coverage is based on the number of write requests and a number of unique rows of memory cells written to based on the write requests. 
     
     
         12 . A memory system comprising:
 an address mapping circuit to receive an input memory address comprising a first set of address bits, the address mapping circuit applying one of a plurality of logic functions to the input memory address to generate a mapped memory address, at least one of the plurality of logic functions using at least a subset of the first set of address bits in two separate operations that respectively determine first and second portions of the mapped memory address, wherein the plurality of logic functions provide different one-to-one mappings from the input memory address to the mapped memory address; and   a hot region guard mechanism to indicate to the address mapping circuit which of the plurality of logic functions to apply to the input memory address to generate the mapped memory address, wherein the hot region guard mechanism tracks statistics representing a number of write requests and a number of unique regions written to based on the write requests.   
     
     
         13 . The memory system of  claim 12 , wherein the address mapping circuit is triggered to select, upon a next memory system restart, a different one of the plurality of logic functions than the currently selected one of the plurality of logic functions, in response to the statistics indicating low coverage by the write requests, and wherein the low coverage is based on the number of write requests and a number of unique rows of memory cells written to based on the write requests. 
     
     
         14 . The memory system of  claim 12  further comprising:
 a dynamic wear leveling function to generate a wear-leveled memory address from at least one of the input memory address and the mapped memory address; and 
 a memory circuit to write data to a memory location in the memory circuit identified by the wear-leveled memory address. 
 
     
     
         15 . The memory system of  claim 12 , wherein the first set of address bits comprises first bits indicating a row address and second bits indicating a column address, and wherein one of the plurality of logic functions generates a mapped memory address with third bits indicating a row address and fourth bits indicating a column address, such that, for consecutive row addresses in an input memory address space, the third bits exhibit decreased row address locality as compared to the first bits, and for consecutive column addresses in the input memory address space, the fourth bits exhibit decreased column address locality as compared to the second bits. 
     
     
         16 . The memory system of  claim 12 , wherein the first set of address bits comprises first bits indicating a row address and second bits indicating a column address, and wherein one of the plurality of logic functions generates a mapped memory address with third bits indicating a row address and fourth bits indicating a column address, the one of the plurality of logic functions generating one or more of the third bits based at least in part on one or more of the second bits, and the one of the plurality of logic functions generating one or more of the fourth bits based at least in part on one or more of the first bits. 
     
     
         17 . The memory system of  claim 12 , wherein one of the plurality of logic functions comprises an offset function that applies a variable deterministic offset to at least a subset of the first set of address bits, the amount of the variable deterministic offset determined based on the value of an offset-determining bit subset of at least one of the first set of address bits. 
     
     
         18 . The memory system of  claim 12 , wherein one of the plurality of logic functions comprises a circular arithmetic shift function of a partial address comprising a first portion of the first set of address bits, and wherein a value of the shift that the circular arithmetic shift function applies to the partial address is a function of a second portion of the first set of address bits. 
     
     
         19 . A memory device comprising:
 an address mapping circuit to receive an input memory address comprising a first set of address bits, the address mapping circuit applying a logic function to the input memory address to generate a mapped memory address, the logic function using at least a subset of the first set of address bits in two separate operations that respectively determine first and second portions of the mapped memory address.   
     
     
         20 . The memory device of  claim 19 , wherein the first set of address bits comprises first bits indicating a row address and second bits indicating a column address, and wherein the logic function generates a mapped memory address with third bits indicating a row address and fourth bits indicating a column address, the logic function generating one or more of the third bits based at least in part on one or more of the second bits, and the logic function generating one or more of the fourth bits based at least in part on one or more of the first bits. 
     
     
         21 . The memory device of  claim 19 , wherein the logic function comprises an XOR function that generates the first portion of the mapped memory address as an XOR output of first and second subsets of selected bits from the first set of address bits. 
     
     
         22 . The memory device of  claim 19 , wherein the logic function comprises a circular arithmetic shift function of a partial address comprising a first portion of the first set of address bits, and wherein a value of the shift that the circular arithmetic shift function applies to the partial address is a function of a second portion of the first set of address bits. 
     
     
         23 . The memory device of  claim 19 , wherein the address mapping circuit comprises multiple logic functions providing different one-to-one mappings from the input memory address to the mapped memory address, and wherein the memory device further comprises a hot region guard mechanism to indicate to the address mapping circuit which of the multiple logic functions to apply to the input memory address to generate the mapped memory address. 
     
     
         24 . The memory device of  claim 19 , wherein the first set of address bits comprises first bits indicating a row address and second bits indicating a column address, and wherein the logic function generates a mapped memory address with third bits indicating a row address and fourth bits indicating a column address, such that, for consecutive row addresses in an input memory address space, the third bits exhibit decreased row address locality as compared to the first bits, and for consecutive column addresses in the input memory address space, the fourth bits exhibit decreased column address locality as compared to the second bits.