3-dimensional nonvolatile memory device and method of manufacturing the same

Abstract

The device includes plural control gates stacked on a substrate, plural first channels, configured to penetrate the control gates, and plural memory layer patterns, each located between the control gate and the first channel, configured to respectively surround the first channel, wherein the memory layer patterns are isolated from one another.

What is claimed is: 
     
         1 . A nonvolatile memory device, comprising:
 plural control gates stacked on a substrate;   plural first channels, configured to penetrate the control gates; and   plural memory layer patterns, each located between the control gate and the first channel, configured to respectively surround the first channel, wherein the memory layer patterns are isolated from one another.   
     
     
         2 . The device of  claim 1 , wherein the first channel includes protrusions configured to protrude between the stacked control gates. 
     
     
         3 . The device of  claim 1 , wherein the first channel includes plural junctions, located between the stacked control gates. 
     
     
         4 . The device of  claim 1 , wherein the memory layer pattern surrounds top and bottom surfaces of the control gate. 
     
     
         5 . The device of  claim 1 , wherein the memory layer pattern is confined between the first channel and the control gate. 
     
     
         6 . The device of  claim 1 , further comprising:
 a pipe gate formed on the substrate; and   a second channel, formed in the pipe gate, configured to connect a pair of first channels.   
     
     
         7 . A method of manufacturing a nonvolatile memory device, comprising:
 alternately forming first material layers and second material layers;   etching the first material layers and the second material layers to form first trenches;   etching the second material layers exposed in the first trenches;   forming a charge trap layer along inner surfaces of the first trenches in which the second material layers are etched;   forming a channel layer on the charge trap layer to form first channels having protrusions protruding between the stacked first material layers;   etching the first material layers and the second material layers to form slits between adjacent first trenches;   etching the charge trap layer exposed in the slits to isolate the charge trap layer of stacked memory cells from one another; and   forming an insulating layer in the slits in which the charge trap layer is etched.   
     
     
         8 . The method of  claim 7 , wherein when the second material layers remain on the inner walls of the slits, the etching of the charge trap layer is performed after removing the remaining second material layers. 
     
     
         9 . The method of  claim 7 , further comprising, forming junctions in the protrusions exposed between the first material layers after the etching of the charge trap layer. 
     
     
         10 . The method of  claim 7 , further comprising, etching the protrusions exposed between the first material layers after the etching of the charge trap layer. 
     
     
         11 . The method of  claim 10 , further comprising, forming junctions in the first channels exposed between the first material layers after the etching of the protrusions. 
     
     
         12 . The method of  claim 7 , further comprising:
 forming control gate regions by removing the first material layers exposed in the slits, after the etching of the charge trap layer; and   forming control gates by forming a conductive layer in the control gate regions.   
     
     
         13 . The method of  claim 12 , wherein the forming of the control gates comprises:
 forming a first metal layer and a second metal layer in the slits in which the control gate regions are formed;   etching the second metal layer formed in the slits except the control gate regions, using a combination of a wet etching process and a dry etching process; and   etching the first metal layer formed in the slits except the control gate regions, using a cleaning process.   
     
     
         14 . The method of  claim 7 , wherein the etching of the charge trap layer comprises etching the protrusions and the charge trap layer surrounding the protrusions to form mold regions. 
     
     
         15 . The method of  claim 14 , further comprising:
 filling the mold regions with an insulating layer to form molds required for forming the control gates, after the etching of the charge trap layer;   removing the first material layers to form the control gate regions; and   forming a conductive layer in the control gate regions to form the control gates.   
     
     
         16 . The method of  claim 15 , wherein the forming of the control gates comprises:
 forming a first metal layer and a second metal layer in the slits in which the control gate regions are formed;   etching the second metal layer formed in the slits except the control gate regions, using a combination of a wet etching process and a dry etching process; and   etching the first metal layer formed in the slits except the control gate regions, using a cleaning process.   
     
     
         17 . The method of  claim 7 , further comprising:
 etching a pipe gate to form a second trench in a position connected to a pair of first trenches, before forming the first material layers and the second material layers;   forming a sacrificial layer in the second trench; and   removing the sacrificial layer after the forming of the first trenches.   
     
     
         18 . The method of  claim 7 , wherein the first material layers and the second material layers are formed of materials having a high etch selectivity ratios against each other. 
     
     
         19 . A method of manufacturing a nonvolatile memory device, comprising:
 alternately forming conductive layers and first sacrificial layers;   etching the conductive layers and the first sacrificial layers to form first trenches;   forming a charge trap layer along inner surfaces of the first trenches;   forming a channel layer on the charge trap layer to form first channels protruding from a substrate;   etching the conductive layers and the second sacrificial layers to form slits between adjacent first trenches;   etching the first sacrificial layers exposed in the slits to expose the charge trap layer;   etching the charge trap layer exposed in the slits to isolate the charge trap layer of stacked memory cells from one another;   forming junctions in the first channels exposed by etching the charge trap layer; and   forming an insulating layer in the slits.   
     
     
         20 . The method of  claim 19 , further comprising:
 forming a pipe gate before the alternately forming of the conductive layers and the first sacrificial layers;   etching the pipe gate to form a second trench in a position connected to a pair of first trenches;   forming a second sacrificial layer in the second trench; and   removing the second sacrificial layer after the forming of the first trenches.