US2013099349A1PendingUtilityA1

Semiconductor device and method of manufacturing the same

Assignee: NOMACHI AKIKOPriority: Oct 19, 2011Filed: Aug 24, 2012Published: Apr 25, 2013
Est. expiryOct 19, 2031(~5.2 yrs left)· nominal 20-yr term from priority
Inventors:Akiko Nomachi
H10P 50/242H10P 50/00H10W 72/20H10W 72/012H10W 20/023H10W 20/0234H10W 20/2125H10W 20/0242H10W 20/217H10W 20/20H10D 62/115
46
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

According to one embodiment, a semiconductor device includes a semiconductor substrate having a first surface and a second surface, and having a LSI on the first surface of the semiconductor substrate, a first insulating layer with an opening, the first insulating layer provided on the first surface of the semiconductor substrate, a conductive layer on the opening, the conductive layer being connected to the LSI, and a via extending from a second surface of the semiconductor substrate to the conductive layer through the opening, the via having a size larger than a size of the opening in a range from the second surface to a first interface between the semiconductor substrate and the first insulating layer, and having a size equal to the size of the opening in the opening.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A method of manufacturing a semiconductor device, the method comprising:
 forming an insulating layer with an opening on a first surface of a semiconductor substrate;   forming a LSI on the first surface of the semiconductor substrate;   forming a conductive layer on the opening, the conductive layer being connected to the LSI;   forming a hole extending from a second surface of the semiconductor substrate to the conductive layer through the opening by selectively etching the semiconductor substrate from the second surface of the semiconductor substrate, the hole having a size larger than a size of the opening in a range from the second surface to an interface between the semiconductor substrate and the insulating layer, and having a size equal to the size of the opening in the opening; and   forming a via in the hole.   
     
     
         2 . The method of  claim 1 , further comprising:
 selectively removing a part of the conductive layer after forming the hole,   wherein the conductive layer comprises a first layer on the insulating layer and a second layer on the first layer, the part of the conductive layer is the first layer, and a size of the conductive layer is smaller than the size of the hole.   
     
     
         3 . The method of  claim 2 ,
 wherein the first layer is a conductive polysilicon layer, and the second layer is a metal silicide layer.   
     
     
         4 . The method of  claim 1 ,
 wherein a condition of etching the semiconductor substrate is constant between from a start of the etching to a time in which the hole reaches to the conductive layer.   
     
     
         5 . The method of  claim 1 ,
 wherein a condition of etching the semiconductor substrate is changed before a time in which the hole reaches to the conductive layer.   
     
     
         6 . The method of  claim 1 , further comprising:
 forming the insulating layer in parallel with forming an element isolation insulating layer which isolates elements in the LSI.   
     
     
         7 . The method of  claim 1 , further comprising:
 forming the insulating layer and the conductive layer in an island manner.   
     
     
         8 . The method of  claim 1 , further comprising:
 forming the conductive layer on the insulating layer in a line manner.   
     
     
         9 . The method of  claim 1 , further comprising:
 forming the insulating layer in a ring manner.   
     
     
         10 . The method of  claim 1 , further comprising:
 forming the opening in a circle or square manner.   
     
     
         11 . A semiconductor device comprising:
 a semiconductor substrate having a first surface and a second surface, and having a LSI on the first surface of the semiconductor substrate;   a first insulating layer with an opening, the first insulating layer provided on the first surface of the semiconductor substrate;   a conductive layer on the opening, the conductive layer being connected to the LSI; and   a via extending from a second surface of the semiconductor substrate to the conductive layer through the opening, the via having a size larger than a size of the opening in a range from the second surface to a first interface between the semiconductor substrate and the first insulating layer, and having a size equal to the size of the opening in the opening.   
     
     
         12 . The device of  claim 1 , further comprising:
 a second insulating layer provided on the first insulating layer, and covering the conductive layer,   wherein a size of the conductive layer is smaller than a size of the opening, and a size of the via is equal to a size of the conductive layer in a range from a second interface between the first and second insulating layers to the conductive layer.   
     
     
         13 . The device of  claim 12 ,
 wherein the conductive layer is a metal silicide.   
     
     
         14 . The device of  claim 11 ,
 wherein a size of the conductive layer is larger than a size of the opening.   
     
     
         15 . The device of  claim 11 ,
 wherein the first insulating layer is a part of an element isolation insulating layer which isolates elements in the LSI.   
     
     
         16 . The device of  claim 11 ,
 wherein each of the first insulating layer and the conductive layer has an island shape.   
     
     
         17 . The device of  claim 11 ,
 wherein the conductive layer has a line shape.   
     
     
         18 . The device of  claim 11 ,
 wherein the first insulating layer has a ring shape.   
     
     
         19 . The device of  claim 11 ,
 wherein the opening has a circle or square shape.   
     
     
         20 . The device of  claim 11 , further comprising:
 a bump on the first surface of the semiconductor substrate,   wherein the bump is provided immediately on the conductive layer, and connected to the conductive layer.

Join the waitlist — get patent alerts

Track US2013099349A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.