Stacked IC Devices Comprising a Workpiece Solder Connected to the TSV

Abstract

A stacked integrated circuit (IC) device with at least one IC die having a top semiconductor surface and a bottom surface and at least one through substrate via (TSV) including a tip protruding beyond the bottom surface to a tip length is provided. The tip has an outer dielectric tip liner, and an electrically conductive portion within the outer dielectric tip liner. A compliant layer is applied to the bottom surface of the IC die. The dielectric tip liner is removed from a distal portion of the tip to expose an electrically conductive tip portion. A solder material is deposited on the exposed distal portion of the tip. The solder material is reflowed and coalesced to form a solder bump on the distal portion of the tip.

We claim: 
     
         1 - 12 . (canceled) 
     
     
         13 . A stacked integrated circuit (IC) device, comprising:
 a first IC die comprising a first substrate including a top semiconductor surface and a bottom surface and at least one through substrate via (TSV) comprising a tip extending from said top semiconductor surface to protrude beyond said bottom surface to a tip length, said tip having an outer dielectric tip liner, and an electrically conductive portion within said outer dielectric tip liner including an electrically contactable distal end, and a compliant layer, thicker than said tip length, attached to said bottom surface of said IC die lateral to said TSV;   a workpiece comprising another IC die or a package substrate attached to said first IC die, and   a solder comprising joint electrically coupling said another IC die or said package substrate to said electrically contactable distal end of said tip of said first IC die.   
     
     
         14 . (canceled) 
     
     
         15 . The stacked IC device of  claim 13 , wherein said first IC die is exclusive of a redistribution layer (RDL) or other pad comprising layer on top or said bottom surface. 
     
     
         16 . The stacked IC device of  claim 13 , wherein said compliant layer does not extend beyond a perimeter of said first IC die. 
     
     
         17 . The stacked IC device of  claim 13 , wherein an area of said older comprising joint is less than or equal to (≦) two (2) times a cross sectional area of said tip. 
     
     
         18 . The stacked IC device of  claim 13 , wherein an area of said solder comprising joint is less than or equal to (≦) a cross sectional area of said tip. 
     
     
         19 . The stacked IC device of  claim 13 , wherein first substrate comprises bulk silicon substrate. 
     
     
         20 . The stacked IC device of  claim 13 , wherein said electrically conductive portion comprises copper. 
     
     
         21 . The stacked IC device of  claim 13 , wherein said workpiece comprises said package substrate.