US2013114602A1PendingUtilityA1

Communicating a message request transaction to a logical device

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Assignee: HARRIMAN DAVIDPriority: Dec 28, 2001Filed: Dec 20, 2012Published: May 9, 2013
Est. expiryDec 28, 2021(expired)· nominal 20-yr term from priority
H04L 69/22G06F 13/4022G06F 13/4282G06F 11/0745H04L 29/0653
57
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Claims

Abstract

A general input/output communication port implements a communication stack that includes a physical layer, a data link layer and a transaction layer. The transaction layer includes assembling a packet header for a message request transaction to one or more logical devices. The packet header includes a format field to indicate the length of the packet header and to further specify whether the packet header includes a data payload, a subset of a type field to indicate the packet header relates to the message request transaction and a message field. The message field includes a message to implement the message request transaction. The message includes at least one message that is selected from a group of messages. The group of messages to include a message to unlock a logical device, a message to reset a logical device, a message to indicate a correctable error condition, a message to indicate an uncorrectable error condition, a message to indicate a fatal error condition, a message to report a bad request packet, a message to indicate power management and a message to emulate an interrupt signal.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . An apparatus comprising:
 an I/O module to:
 assemble a transaction layer packet header of a packet, wherein the header is to include a format field, a type field, and a length field; and 
 send the packet over an interconnect comprising one or more serial point-to-point links, wherein routing of the packet is to be based at least in part on the type field. 
   
     
     
         2 . The apparatus of  claim 1 , wherein the interconnect comprises at least one of a physical layer to support a Peripheral Component Interconnect Express (PCIe) protocol layer, a physical layer including one or more protocols. 
     
     
         3 . The apparatus of  claim 1 , wherein the interconnect comprises a PCIe-compliant interconnect. 
     
     
         4 . The apparatus of  claim 1 , wherein the packet includes a data payload and identification of packet format is based at least in part on values of the format field and type field. 
     
     
         5 . The apparatus of  claim 4 , wherein the length field is to indicate a length of data included in the payload. 
     
     
         6 . The apparatus of  claim 1 , wherein the format field is to comprise at least two bits. 
     
     
         7 . The apparatus of  claim 1 , wherein the type field is to comprise six bits. 
     
     
         8 . The apparatus of  claim 1 , wherein the packet comprises a message packet and the header is to include a message field. 
     
     
         9 . The apparatus of  claim 8 , wherein the message field is to indicate whether completion is required. 
     
     
         10 . The apparatus of  claim 1 , wherein the header is further to include a transaction identifier comprising a requester identifier and tag. 
     
     
         11 . The apparatus of  claim 10 , wherein the requester identifier is to identify a bus number, a device number, and a function number corresponding to the device, and a value of the tag is to be unique for all outstanding requests of the device 
     
     
         12 . The apparatus of  claim 10 , wherein the tag is unique for all outstanding requests of the I/O module. 
     
     
         13 . The apparatus of  claim 1 , wherein the header further includes an attributes field. 
     
     
         14 . The apparatus of  claim 13 , wherein the packet is included in a transaction and the attribute field is to identify one or more characteristics of the transaction. 
     
     
         15 . The apparatus of  claim 14 , wherein the one or more characteristics include an ordering attribute. 
     
     
         16 . The apparatus of  claim 1 , wherein the packet comprises a completion packet. 
     
     
         17 . An apparatus comprising:
 an I/O module to:
 receive a packet from a device over a an interconnect comprising one or more serial point-to-point links, wherein the packet includes a transaction layer packet header that includes a format field, a type field, and a length field; and 
 route the packet based at least in part on the type field. 
   
     
     
         18 . The apparatus of  claim 17 , wherein the interconnect comprises at least one of a physical layer to support a Peripheral Component Interconnect Express (PCIe) protocol layer, a physical layer including one or more protocols. 
     
     
         19 . The apparatus of  claim 17 , wherein the interconnect comprises a PCIe-compliant interconnect 
     
     
         20 . The apparatus of  claim 17 , wherein the I/O module is further configured to identify format of the packet header from a value of the format field. 
     
     
         21 . The apparatus of  claim 17 , wherein the packet header further includes a requester identifier identifying the device. 
     
     
         22 . The apparatus of  claim 17 , wherein the packet is included in a transaction comprising a request and a completion. 
     
     
         24 . A system comprising:
 a Peripheral Component Interconnect Express (PCIe)-compliant interconnect;   a first device; and   a second device wherein the second device is communicatively coupled to the first device using the interconnect and the second device is configured to:
 assemble a transaction layer packet header of a packet in a transaction, wherein the header is to include a format field, a type field, and a length field; and 
 communicate the packet over the interconnect to the first device, wherein routing of the packet is based at least in part on the type field. 
   
     
     
         25 . The system of  claim 24 , wherein the first device is configured to complete the transaction using information included in the packet. 
     
     
         26 . The system of  claim 24 , wherein the first device comprises a root controller. 
     
     
         27 . The system of  claim 24 , wherein the first device comprises a switch. 
     
     
         28 . The system of  claim 24 , wherein the first device comprises a bridge. 
     
     
         29 . A method comprising:
 assembling a transaction layer packet header of a packet, wherein the header is to include a format field, a type field, and a length field; and   sending the packet over an interconnect comprising one or more serial point-to-point links, wherein routing of the packet is based at least in part on the type field.   
     
     
         30 . The method of  claim 29 , wherein the interconnect comprises at least one of a physical layer to support a Peripheral Component Interconnect Express (PCIe) protocol layer, a physical layer including one or more protocols. 
     
     
         31 . The method of  claim 29 , wherein the interconnect comprises a PCIe-compliant interconnect. 
     
     
         32 . The method of  claim 29 , wherein the packet includes a data payload and identification of packet format is based at least in part on values of the format field and type field. 
     
     
         33 . The method of  claim 29 , wherein the packet is a first packet, the method further comprising:
 receiving a second packet from a device over the interconnect, wherein the second packet includes a transaction layer packet header including a format field, a type field, and a length field; and   processing the packet based at least in part on the type field.

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