Platform communication protocol

Abstract

A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state.

1 . An apparatus comprising:
 logic to:
 identify a time window corresponding to an opportunity for devices to interact with a system component; 
 send a signal to a device over an interconnect comprising one or more serial point-to-point differential links, wherein the signal is to indicate the time window to the device. 
   
     
     
         2 . The apparatus of  claim 1 , wherein the time window corresponds to an active state of the system component. 
     
     
         3 . The apparatus of  claim 1 , wherein timing window corresponds to power management state transitions affecting the system component. 
     
     
         4 . The apparatus of  claim 1 , wherein the signal comprises an in band signal. 
     
     
         5 . The apparatus of  claim 4 , wherein the signal comprises a message signal that is to indicate a present power state of the system component. 
     
     
         6 . The apparatus of  claim 5 , wherein the message comprises a packet including an indicator that the packet communicates time window information. 
     
     
         7 . The apparatus of  claim 1 , wherein the signal comprises a sideband signal. 
     
     
         8 . The apparatus of  claim 7 , wherein the signal comprises a Peripheral Component Interconnect Express (PCIe)-compliant WAKE# signal. 
     
     
         9 . The apparatus of  claim 7 , where in the logic is further to send an in-band signal to a second device, wherein the in-band signal is to indicate the time window. 
     
     
         10 . The apparatus of  claim 1 , wherein the system component comprises a system microprocessor. 
     
     
         11 . The apparatus of  claim 1 , wherein the system component is included in a root complex. 
     
     
         12 . The apparatus of  claim 1 , wherein the interconnect comprises at least one of a physical layer to support a PCIe protocol layer, and a physical layer including one or more protocols. 
     
     
         13 . The apparatus of  claim 1 , wherein the interconnect comprises a PCIe-compliant interconnect. 
     
     
         14 . The apparatus of  claim 1 , wherein the time window corresponds to an interrupt affecting the system component. 
     
     
         15 . The apparatus of  claim 1 , wherein the time window corresponds to a traffic cycle of the system component. 
     
     
         16 . An apparatus comprising:
 logic to:
 receive a signal over an interconnect comprising one or more serial point-to-point differential links; and 
 interpret the signal to identify a time window representing an opportunity to time interactions with a system component. 
   
     
     
         17 . The apparatus of  claim 16 , wherein the logic is further to send data over the interconnect to the system component based at least in part on the indicated time window. 
     
     
         18 . The apparatus of  claim 17 , wherein the sending of data is to correspond to an active state of the system component. 
     
     
         19 . The apparatus of  claim 16 , wherein the signal comprises a sideband signal. 
     
     
         20 . The apparatus of  claim 19 , wherein the signal comprises a Peripheral Component Interconnect Express (PCIe)-compliant WAKE# signal. 
     
     
         21 . The apparatus of  claim 16 , wherein the signal comprises an in-band message. 
     
     
         22 . The apparatus of  claim 16 , wherein the interconnect comprises at least one of a physical layer to support a PCIe protocol layer, and a physical layer including one or more protocols. 
     
     
         23 . The apparatus of  claim 16 , wherein the interconnect comprises a PCIe-compliant interconnect. 
     
     
         24 . An apparatus comprising:
 a root complex to:
 determine availability of a wake signal for a particular one of a plurality of devices communicatively coupled to the root complex at least in part using a serial point-to-point differential link, wherein the wake signal is to communicate a hint to indicate an opportunity for the particular device to substantially align interactions of the particular device with a system component with a power management state transition of the system component, wherein determining that the wake signal is unavailable for the particular device is to cause the hint to be communicated to the particular device as a message, and determining the availability of the wake signal comprises includes determining whether the particular device is at least partially accessible via sideband signaling; and 
 send the hint to the particular device over the link when the link is in an operational power state. 
   
     
     
         25 . The apparatus of  claim 24 , wherein the link comprises a PCIe-compliant link. 
     
     
         26 . The apparatus of  claim 24 , wherein the wake signal comprises a sideband PCIe-compliant WAKE# signal and the message comprises an in-band message. 
     
     
         27 . The apparatus of  claim 24 , wherein the operational power state comprises an L0 state. 
     
     
         28 . A method comprising:
 determining, for a device, a hint to indicate a time window representing an opportunity for the device to align interaction of the device with an active state of a system component;   sending the hint to the device over a serial point-to-point interconnect; and   receiving data from the device during the time window.   
     
     
         29 . The method of  claim 28 , wherein the interconnect comprises a PCIe-compliant interconnect. 
     
     
         30 . The method of  claim 28 , wherein the hint is one of a sideband signal and an in-band message. 
     
     
         31 . The method of  claim 30 , wherein the in-band message is to be determined for the device when the sideband signal is unavailable for the interconnect. 
     
     
         32 . The method of  claim 30 , wherein the signal comprises a PCIe-compliant WAKE# signal. 
     
     
         33 . A system comprising:
 a serial point-to-point interconnect;   a first device; and   a second device wherein the second device is communicatively coupled to the first device using the interconnect and the second device includes logic to:
 send a signal to the first device over the interconnect, wherein the signal is to indicate a time window representing an opportunity for the first device to align interaction of the device with a microprocessor. 
   
     
     
         34 . The system of  claim 33 , wherein the interconnect comprises a PCIe-compliant interconnect. 
     
     
         35 . The system of  claim 33 , wherein the second device comprises a root complex. 
     
     
         36 . The system of  claim 33 , wherein the second device comprises a switch. 
     
     
         37 . The system of  claim 33 , wherein the first device is adapted to receive and interpret a version of the signal comprising a PCIe-compliant WAKE# signal. 
     
     
         38 . The system of  claim 33 , wherein the first device is adapted to receive and interpret a version of the signal comprising an in-band message. 
     
     
         39 . The system of  claim 33 , further comprising a third device, wherein the signal to the first device comprises a PCIe-compliant WAKE# signal and the logic is further to send an in-band message to the third device, wherein the in-band message is to indicate the time window.