Semiconductor device including vertical transistor and method for manufacturing the same

Abstract

A semiconductor device including a vertical transistor and a method for manufacturing the same may reduce a cell area in comparison with a conventional layout of 8F2 and 6F2. Also, the method does not require forming a bit line contact, a storage node contact or a landing plug, thereby decreasing the process steps. The semiconductor device including a vertical transistor comprises: an active region formed in a semiconductor substrate; a bit line disposed in the lower portion of the active region; a word line buried in the active region; and a capacitor to disposed over the upper portion of the active region and the word line,

1 . A semiconductor device including a vertical transistor, the device comprising:
 an active region formed in a semiconductor substrate;   a bit line disposed in a lower portion of the active region;   a word line buried in the active region, the word line being formed inside of the active region or formed penetrating the active region; and   a capacitor disposed over an upper portion of the active region and the word line, the capacitor being coupled to the bit line via the active region.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein to the word line and the active region are in contact and defining a step difference. 
     
     
         3 . The semiconductor device according to  claim 1 , wherein the word line and the active region are in contact with substantially no step difference. 
     
     
         4 . The semiconductor device according to  claim 1 , wherein the cross-sectional shape of the word line is rectangular or oval. 
     
     
         5 . The semiconductor device according to  claim 1 , wherein the active region has a rectangular pillar shape or a cylindrical column shape. 
     
     
         6 . The semiconductor device according to  claim 1 , further comprising a storage node contact coupled between upper portion of the active region and the lower portion of the capacitor. 
     
     
         7 . The semiconductor device according to  claim 1 , wherein the word line is buried in a middle part of the active region or at one sidewall of the active region. 
     
     
         8 . The semiconductor device according to  claim 1 , wherein an upper side end portion of the word line extends to a level lower than an upper side end portion of the active region. 
     
     
         9 . The semiconductor device according to  claim 1 , wherein the bit line and the word line extend in a perpendicular direction from each other. 
     
     
         10 . The semiconductor device according to  claim 1 , further comprising a first insulating film disposed between the active regions. 
     
     
         11 . The semiconductor device according to  claim 1 , further comprising a word line insulating film including an oxide film disposed between the active region and the word line. 
     
     
         12 . The semiconductor device according to  claim 1 , wherein the bit line includes any of a metal and an ion-implanting region. 
     
     
         13 . The semiconductor device according to  claim 1 , further comprising a second insulating film between the word line and the capacitor. 
     
     
         14 . The semiconductor device according to  claim 10 , further comprising an protective film disposed between the active region and the first insulating film, and disposed parallel with the bit line. 
     
     
         15 - 30 . (canceled) 
     
     
         31 . The semiconductor device according to  claim 1 , wherein the capacitor is formed to have at least one of a concave type, a cylinder type and a pillar type. 
     
     
         32 . A semiconductor device comprising:
 a vertical word line formed over a substrate;   a semiconductor pattern at least partly surrounding a sidewall of the vertical word line;   a bit line formed at a first end of the vertical word line; and   a storage node electrode formed at a second end of the vertical word line;   wherein the bit line and the storage node electrode are electrically coupled to each other through the semiconductor pattern, and   wherein the vertical word line is formed inside of the semiconductor pattern or formed penetrating the semiconductor pattern.   
     
     
         33 . The semiconductor device of  claim 32 , wherein the semiconductor pattern defines an active region for a unit cell. 
     
     
         34 . The semiconductor device of  claim 32 , wherein the vertical word line extends to a first neighboring unit cell along a first direction, and wherein the bit line extends to a second neighboring unit cell along a second direction perpendicular to the first direction. 
     
     
         35 . The semiconductor device of  claim 34 , wherein the vertical word line has a step difference at the first end along the first direction between a first region where the bit line is formed and a second region where the bit line is not formed, or the word line is substantially flat at the first end along the first direction. 
     
     
         36 . The semiconductor device of  claim 32 , wherein the vertical word line is buried in a middle part of the semiconductor pattern or at one sidewall of the semiconductor pattern.