Dynamically controllable drive circuit for parallel array of light emitting diodes

Abstract

The present invention relates to a parallel light emitting diode (“LED”) drive circuit and provides a drive circuit configured to drive a parallel array of LEDs. The drive circuit comprises: a switching control signal generator, a plurality of switches, a plurality of sampling resistors, and a plurality of chopper amplifiers. Each switch is coupled to a respective LED in the LED array. Each chopper operational amplifier configured to receive a reference voltage and a switching control signal generated by the switching control signal generator and generate an input offset voltage. Each chopper operational amplifier includes a differential amplifier including an input transistor pair and a current mirror transistor pair, of which the electrical positions can be reserved when the switching control signal is switched between a first state and a second state, wherein the offset voltage, which causes the lightness mismatching in a parallel LED circuit, can be cancelled.

1 - 17 . (canceled) 
     
     
         18 . A switching control signal generator configured to deliver a switching control signal having a period distributed between a first state and a second state to control an operation of a plurality of light emitting diodes, comprising:
 an oscillator configured to receive a square wave signal;   a first D flip-flop having a clock input terminal configured to receive the square wave signal, wherein a D input terminal of the first D flip-flop is shorted with a negative output terminal of the first D flip-flop;   a second D flip-flop having a clock input terminal connected to a clock signal output terminal of the oscillator, wherein a D input terminal of the second D flip-flop is shorted with a negative output terminal of the second D flip-flop, and   a logic gate having a first input terminal connected to a positive output terminal of the second D flip-flop, a second input terminal connected to a positive output terminal of the first D flip-flop, and an output terminal configured to deliver a switching control signal having a period distributed between a first state and a second state.   
     
     
         19 . The switching control signal generator of  claim 18 , wherein the switching control signal alternates between the first state and the second state. 
     
     
         20 . The switching control signal generator of  claim 19 , wherein the switching control signal has a duty cycle of about 50%. 
     
     
         21 . The switching control signal generator of  claim 18 , wherein the first D flip-flop is configured to perform frequency reduction of the square wave signal. 
     
     
         22 . The switching control signal generator of  claim 21 , wherein the frequency reduction of the square wave signal is by an even factor. 
     
     
         23 . The switching control signal generator of  claim 18 , wherein the second D flip-flop is configured to perform a frequency reduction of the clock signal. 
     
     
         24 . The switching control signal generator of  claim 23 , wherein the frequency reduction of the clock signal is by an even factor. 
     
     
         25 . A drive circuit configured to drive a parallel array of light emitting diodes (LEDs), comprising:
 a switching control signal generator including:
 a first D flip-flop having a clock input terminal configured to receive a square wave signal, wherein a D input terminal of the first D flip-flop is shorted with a negative output terminal of the first D flip-flop, 
 a second D flip-flop having a clock input terminal configured to receive a clock signal, wherein a D input terminal of the second D flip-flop is shorted with a negative output terminal of the second D flip-flop, and 
 a logic gate having a first input terminal connected to a positive output terminal of the second D flip-flop, a second input terminal connected to a positive output terminal of the first D flip-flop, and an output terminal configured to deliver a switching control signal; 
   a plurality of switches, each configured to be coupled to a respective LED in a parallel array of LEDs; and   a plurality of chopper operational amplifiers, each chopper operational amplifier configured to receive a reference voltage and the switching control signal and generate an input offset voltage configured to control a respective switch in the plurality of switches.   
     
     
         26 . The drive circuit of  claim 25 , wherein each chopper operational amplifier includes a differential amplifier including an input transistor pair and a current mirror transistor pair. 
     
     
         27 . The drive circuit of  claim 26 , wherein the input transistor pair and current mirror transistor pair are mismatched, and wherein when the switching control signal is switched between a first state and a second state, electrical positions of the input transistor pair switch and electrical positions of the current mirror transistor pair switch to thereby cause a reversing of polarity of an input offset voltage of the chopper operational amplifier. 
     
     
         28 . The drive circuit of  claim 25 , wherein the switching control signal alternates between a first state and a second state. 
     
     
         29 . The drive circuit of  claim 28 , wherein the switching control signal has a duty cycle of about 50%. 
     
     
         30 . The drive circuit of  claim 25 , wherein the first D flip-flop is configured to perform frequency reduction of the square wave signal. 
     
     
         31 . The drive circuit of  claim 30 , wherein the frequency reduction of the square wave signal is by an even factor. 
     
     
         32 . The drive circuit of  claim 25 , wherein the second D flip-flop is configured to perform a frequency reduction of the clock signal. 
     
     
         33 . The drive circuit of  claim 32 , wherein the frequency reduction of the clock signal is by an even factor.