Fault Tolerant Integrated Circuit Architecture

Abstract

The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function. The assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation.

It is claimed: 
     
         1 . An apparatus comprising:
 a communication element;   a plurality of composite circuit elements coupled to the communication element, each composite circuit element comprising a uniform element interface and a circuit element of a plurality of circuit element types, a first composite circuit element of the plurality of composite circuit elements having a first action, a second composite circuit element of the plurality of composite circuit elements having a second action, a third composite circuit element of the plurality of composite circuit elements having the first action, wherein the second composite circuit element has a programmable first data link to the first composite circuit element for performance of a first function or has an programmable second data link to the third composite circuit element for performance of the first function.   
     
     
         2 . The apparatus of  claim 1 , further comprising:
 a state machine element coupled to the plurality of communication elements, the state machine element, in response to an unavailability of the first composite circuit element, to program the third composite circuit element for the first action and to program the second data link between the second composite circuit element and the third composite circuit element.   
     
     
         3 . The apparatus of  claim 2 , wherein the plurality of circuit element types comprises at least one of the following circuit element types: a plurality of configurable element types, a memory element type, a plurality of communication element types; and a plurality of non-configurable element types. 
     
     
         4 . The apparatus of  claim 1 , wherein each uniform element interface comprises:
 a first memory coupled to the corresponding circuit element, the first memory to store at least one configuration of the corresponding circuit element;   an element controller coupled to the corresponding circuit element; and   a second memory coupled to the corresponding circuit element, the second memory comprising a plurality of input queues for data input to the corresponding circuit element.   
     
     
         5 . The apparatus of  claim 4 , wherein the first memory further is to store a plurality of contexts, each context of the plurality of contexts specifying a selected configuration of a plurality of configurations of the corresponding circuit element, and either or both one or more data input sources or one or more data output destinations. 
     
     
         6 . The apparatus of  claim 4 , wherein the uniform element interface further comprises:
 a third memory coupled to the circuit element, the third memory comprising a plurality of output queues for data output from the circuit element.   
     
     
         7 . The apparatus of  claim 1 , wherein the communication element comprises:
 a corresponding element interface; and   a corresponding communication circuit element.   
     
     
         8 . The apparatus of  claim 1 , wherein the communication element is both to route at least one first data word and to switch at least one second data word. 
     
     
         9 . The apparatus of  claim 1 , wherein the communication element comprises an intercluster queue to transfer a data word between adjacent pluralities of composite circuit elements. 
     
     
         10 . The apparatus of  claim 1 , wherein each uniform element interface comprises:
 a first memory coupled to the circuit element, the first memory to store a plurality of configurations as corresponding contexts;   an element controller coupled to the circuit element;   a second memory coupled to the circuit element, the second memory comprising a plurality of input queues for data input to the circuit element; and   a third memory coupled to the circuit element, the third memory comprising a plurality of output queues for data output from the circuit element.   
     
     
         11 . The apparatus of  claim 1 , further comprising a plurality of communication elements, wherein the plurality of communication elements further comprise:
 a queue to buffer a data word from a first array of the plurality of composite circuit elements and to transfer the data word to an adjacent second array of the plurality of composite circuit elements; and   a full interconnect element coupled to the first plurality of composite circuit elements and to the queue, the full interconnect element to couple any output of a composite circuit element of the first plurality of composite circuit elements to any input of another composite circuit element of the first plurality of composite circuit elements or to the queue.   
     
     
         12 . The apparatus of  claim 1 , wherein the plurality of communication elements further comprise:
 a message manager circuit coupled to the state machine element, the message manager circuit both to route at least one first data word and to switch at least one second data word.   
     
     
         13 . The apparatus of  claim 1 , wherein the communication element is to route or switch at least one data word between a first array of the plurality of composite circuit elements and a second array of the plurality of composite circuit elements. 
     
     
         14 . The apparatus of  claim 1 , wherein the communication element is to buffer at least one data word from a first array of the plurality of composite circuit elements and to transfer the at least one data word to an adjacent second array of the plurality of composite circuit elements 
     
     
         15 . The apparatus of  claim 1 , further comprising:
 a message manager circuit coupled to the state machine element, the message manager circuit to provide a communication interface to an external bus or an external memory.   
     
     
         16 . An apparatus comprising:
 a state machine element;   an interconnect element;   an intercluster queue coupled to the interconnect element, the intercluster queue to buffer a data word from a first plurality of composite circuit elements and to transfer the data word to an adjacent second plurality of composite circuit elements; and   the first plurality of composite circuit elements coupled to the interconnect element, each composite circuit element comprising an element interface and a circuit element of a plurality of circuit element types, a first composite circuit element of the first plurality of composite circuit elements having a first action, a second composite circuit element of the first plurality of composite circuit elements having a second action, the first composite circuit element having a programmable first data link to the second composite circuit element through the interconnect element.   
     
     
         17 . The apparatus of  claim 16 , further comprising:
 a communication element coupled to the interconnect element, the communication element both to route at least one first data word and to switch at least one second data word.   
     
     
         18 . The apparatus of  claim 16 , wherein each uniform element interface comprises:
 a first memory coupled to the corresponding circuit element, and when the corresponding circuit element is configurable, the first memory to store at least one configuration of the corresponding circuit element;   an element controller coupled to the corresponding circuit element;   a second memory coupled to the corresponding circuit element, the second memory comprising a plurality of input queues for data input to the corresponding circuit element; and   a third memory coupled to the corresponding circuit element, the third memory comprising a plurality of output queues for data output from the corresponding circuit element.   
     
     
         19 . The apparatus of  claim 18 , wherein the interconnect element is to couple any output queue of a composite circuit element of the first plurality of composite circuit elements to any input queue of another composite circuit element of the first plurality of composite circuit elements or to the intercluster queue. 
     
     
         20 . An apparatus comprising:
 a plurality of circuit arrays, each circuit array of the plurality of circuit arrays comprising:   an interconnect element;   a plurality of communication elements coupled to the interconnect element, the plurality of communication elements to transfer data from a first circuit array to a second circuit array of the plurality of circuit arrays;   a plurality of composite circuit elements coupled to the interconnect element, each composite circuit element comprising an element interface and a circuit element of a plurality of circuit element types, a first composite circuit element of the plurality of composite circuit elements having a first action, a second composite circuit element of the plurality of composite circuit elements having a second action, the first composite circuit element having a programmed first data link to the second composite circuit element through the interconnect element.