Power semiconductor device driving circuit

Abstract

A power semiconductor device driving circuit includes a gate control terminal, which is provided at a position separated from a drain terminal of a power semiconductor device by a predetermined distance so that electric discharge is generated between the drain terminal and the gate control terminal at the time of generation of surge. A surge voltage is applied to the gate control terminal due to this discharge, the gate of the power semiconductor device is charged to turn on and absorb the surge energy. Thus it becomes possible to suppress the surge voltage applied to the drain terminal and prevent breakdown of the power semiconductor device.

What is claimed is: 
     
         1 . A power semiconductor device driving circuit comprising:
 a power semiconductor device formed of a semiconductor switching device, which controls a current supplied to a first terminal and a second terminal based on a gate voltage applied to a gate terminal, the first terminal and the second terminal being a high-side terminal and a low-side terminal;   a gate driving circuit for controlling the gate voltage applied to the gate terminal of the power semiconductor device;   a discharge terminal provided at a position separated from the first terminal by a predetermined distance to cause a discharge between the first terminal when the voltage at the first terminal rises by generation of surge and reaches a dielectric breakdown voltage; and   a gate charge circuit, which turns on the power semiconductor device by charging a gate of the power semiconductor device based on the discharge between the first terminal and the discharge terminal and lowers the voltage of the first terminal by a current flowing between the first terminal and the second terminal.   
     
     
         2 . The power semiconductor device driving circuit according to  claim 1 , wherein:
 the discharge terminal includes a gate control terminal;   the gate charge circuit includes a resistor provided between the gate control terminal and the gate terminal of the power semiconductor device; and   the gate of the power semiconductor device is charged by the surge voltage, which is generated by the surge, applied to the gate control terminal and applied to the gate terminal through the resistor.   
     
     
         3 . The power semiconductor device driving circuit according to  claim 1 , wherein:
 the discharge terminal includes a gate control terminal provided in the gate driving circuit; and   the gate charging circuit includes a voltage holding circuit, which is provided in the gate driving circuit and turns on the power semiconductor device by holding the gate terminal in a state that a predetermined voltage is applied to the gate terminal for a predetermined period when the surge voltage is applied to the gate control terminal.   
     
     
         4 . The power semiconductor device driving circuit according to  claim 3 , wherein:
 the discharge terminal further includes another gate control terminal provided outside the gate driving circuit;   the gate charge circuit includes a resistor provided between the another gate control terminal and the gate terminal of the power semiconductor device; and   the gate of the power semiconductor device is charged by the surge voltage, which is generated by the surge, applied to the another gate control terminal and applied to the gate terminal through the resistor.   
     
     
         5 . The power semiconductor device driving circuit according to  claim 1 , wherein:
 the discharge terminal is a connection terminal connected to the second terminal;   voltage dividing resistors are provided between the second terminal and the connection terminal to input a voltage divided by the voltage dividing resistors to the gate control terminal provided in the gate driving circuit; and   the gate charging circuit includes a voltage holding circuit, which turns on the power semiconductor device by holding the gate terminal in a state that a predetermined voltage is applied to the gate terminal for a predetermined period when the voltage divided by the voltage dividing resistors is applied to the gate control terminal.   
     
     
         6 . The power semiconductor device driving circuit according to  claim 3 , further comprising:
 an auxiliary power source for supplying a voltage, which is smaller than a voltage required to fully turn on the power device,   wherein the gate charging circuit includes a switch, which is turned on during the predetermined period by the voltage holding circuit, and   the gate charging circuit applies an auxiliary power voltage supplied by the auxiliary power source to the gate terminal as the predetermined voltage when the switch is turned on.   
     
     
         7 . An electric system comprising:
 a full-bridge circuit including two circuits, each of which includes a pair of power semiconductor devices, each of which is connected to the power semiconductor device driving circuit according to  claim 1 , the full-bridge circuit generating an AC voltage; and   a load connected between a junction of one pair of the power semiconductor devices connected in series in one of the two circuits and a junction of another pair of the power semiconductor devices connected in series in another of the two circuits, the load being driven by the AC voltage of the full-bridge circuit.