Method and apparatus for refresh management of memory modules

Abstract

One embodiment sets forth an interface circuit configured to manage refresh command sequences that includes a system interface adapted to receive a refresh command from a memory controller, clock frequency detection circuitry configured to determine the timing for issuing staggered refresh commands to two or more memory devices coupled to the interface circuit based on the refresh command received from the memory controller, and at least two refresh command sequence outputs configured to generate the staggered refresh commands for the two or more memory devices

1 . (canceled) 
     
     
         2 . An interface circuit, comprising:
 a system interface circuit configured to receive from a memory controller a refresh command for a first number of emulated dynamic random access memory (DRAM) devices;   a measurement unit configured to perform measurements of one or more pins of the interface circuit, wherein the measurements include (i) first timing response characteristics of a particular DRAM device of a different, second number of physical DRAM devices, and (ii) second timing response characteristics of a different DRAM device of the second number of physical DRAM devices;   a calculation unit configured to:
 receive information related to the first measured timing response characteristics and the second measured timing response characteristics from the measurement unit; and 
 determine, based at least in part on the information received from the measurement unit, timing for issuing a sequence of staggered refresh commands to the second number of physical DRAM devices that appear to the memory controller as the first number of emulated DRAM devices, wherein the sequence of staggered refresh commands to the second number of physical DRAM devices completes in a refresh cycle time based on the refresh command from the memory controller for the first number of emulated DRAM devices; and 
   a scheduler configured to order staggered refresh commands for the second number of physical DRAM devices based on the timing determined by the calculation unit   
     
     
         3 . The interface circuit of  claim 2 , wherein:
 the measurement unit is further configured to determine a configuration of the second number of physical DRAM devices, wherein the configuration includes one or more of size, number of ranks, or memory word organization associated with the second number of physical DRAM devices   
     
     
         4 . The interface circuit of  claim 2 , wherein the measurement unit is further configured to perform a series of measurements to determine timing response characteristics of each of the second number of physical DRAM devices. 
     
     
         5 . The interface circuit of  claim 2 , wherein the measurement unit is further configured to perform a series of measurements to determine timing responses of the particular DRAM device at selected logic threshold levels. 
     
     
         6 . The interface circuit of  claim 2 , wherein the measurement unit is further configured to perform a series of measurements to determine a timing response of the particular DRAM device at a peak detected voltage change, a duration and a response ring. 
     
     
         7 . The interface circuit of  claim 2 , wherein the measurement unit is further configured to perform a series of measurements to determine an operating temperature of each of the second number of physical DRAM devices. 
     
     
         8 . The interface circuit of  claim 2 , wherein the staggered refresh cycles are staggered by equal amounts of time within a single refresh cycle associated with the refresh command received from the memory controller. 
     
     
         9 . The interface circuit of  claim 2 , wherein the calculation unit is configured to determine N staggered refresh cycles for 2*N DRAM devices coupled to the interface circuit that are staggered by an amount of time equal to approximately an N-th of a single refresh cycle associated with the refresh command received from the memory controller, wherein N is a number greater than one. 
     
     
         10 . The interface circuit of  claim 2 , wherein the calculation unit is configured to dynamically determine, at a time subsequent to applying power to the second number of physical DRAM devices, timing for issuing a sequence of staggered refresh commands. 
     
     
         11 . The interface circuit of  claim 2 , wherein the system interface further comprises a memory address signal interface, a memory control signal interface, a memory clock signal interface, and a memory data signal interface. 
     
     
         12 . The interface circuit of  claim 2 , further comprising emulation logic configured to emulate an interface protocol of each of the first number of emulated DRAM devices. 
     
     
         13 . The interface circuit of  claim 2 , wherein the second number of physical DRAM devices are arranged in one or more stacks, and a staggered refresh cycle is transmitted to two or more memory devices residing within the same stack. 
     
     
         14 . The interface circuit of  claim 13 , wherein the second number of physical DRAM devices are arranged in one stack, and the interface circuit is integrated within the one stack. 
     
     
         15 . The interface circuit of  claim 2 , wherein the interface circuit and the second number of physical DRAM device are included in a dual in-line memory module. 
     
     
         16 . The interface circuit of  claim 2 , wherein the measurements are analog signal measurements. 
     
     
         17 . The memory module of  claim 2 , wherein a time difference between a start time of each of the sequence of staggered refresh commands relative to the refresh command from the memory controller differs for each of the staggered refresh commands. 
     
     
         18 . A memory module comprising:
 a first number of physical memory devices; and   an interface circuit comprising:
 a system interface circuit configured to receive from a memory controller a refresh command for a second number of emulated memory devices; 
 a measurement unit configured to perform measurements of one or more pins of the interface circuit, wherein the measurements include (i) first timing response characteristics of a particular memory device of the first number of physical memory devices, and (ii) second timing response characteristics of a different memory device of the first number of physical memory devices; 
 a calculation unit configured to:
 receive information related to the first measured timing response characteristics and the second measured timing response characteristics from the measurement unit; and 
 determine, based at least in part on the information received from the measurement unit, timing for issuing a sequence of staggered refresh commands to the first number of physical memory devices that appear to the memory controller as the second number of emulated devices, wherein the sequence of staggered refresh commands to the first number of physical memory devices completes in a refresh cycle time based on the refresh command from the memory controller for the second number of emulated memory devices; and 
 
 a scheduler configured to order staggered refresh commands for the first number of physical memory devices based on the timing determined by the calculation unit. 
   
     
     
         19 . The memory module of  claim 18 , wherein the calculation unit is configured to dynamically determine, at a time subsequent to applying power to the first number of physical memory devices, timing for issuing a sequence of staggered refresh commands. 
     
     
         20 . A memory module comprising:
 2*N physical memory devices each having a capacity of M; and   an interface circuit comprising:
 a system interface circuit configured to receive from a memory controller a refresh command for two emulated memory devices, wherein each of the two emulated memory devices has a capacity of N*M; 
 a measurement unit configured to perform measurements of one or more pins of the interface circuit, wherein the measurements include (i) first timing response characteristics of a particular DRAM device of the 2*N physical DRAM devices, and (ii) second timing response characteristics of a different DRAM device of the 2*N physical DRAM devices; 
 a calculation unit configured to:
 receive information related to the first measured timing response characteristics and the second measured timing response characteristics from the measurement unit; and 
 determine, based at least in part on the information received from the measurement unit, timing for issuing a sequence of staggered refresh commands to the 2*N physical memory devices that appear to the memory controller as the two emulated devices, wherein the sequence of staggered refresh commands to the 2*N physical memory devices completes in a refresh cycle time based on the refresh command from the memory controller for the two emulated memory devices; and 
 
   a scheduler configured to order staggered refresh commands for the 2*N physical memory devices based on the timing determined by the calculation unit.   
     
     
         21 . The memory module of  claim 20 , further comprising emulation logic configured to emulate an interface protocol of the two emulated memory devices each having a capacity of N*M.