Interposer and semiconductor package with noise suppression features

Abstract

Interposer and semiconductor package embodiments provide for the isolation and suppression of electronic noise such as EM emissions in the semiconductor package. The interposer includes shield structures in various embodiments, the shield structures blocking the electrical noise from the noise source, from other electrical signals or devices. The shields include solid structures and some embodiments and decoupling capacitors in other embodiments. The coupling structures includes multiple rows of solder balls included in strips that couple the components and surround and contain the source of electrical noise.

What is claimed is: 
     
         1 . An interposer for connecting a semiconductor die to a printed circuit board, said interposer comprising:
 a body having opposed first and second surfaces, wherein a facing surface of said semiconductor die is joined to said first surface of said interposer by at least a strip of multiple rows of solder balls that are disposed on, and extend along, said facing surface on outer portions of said semiconductor die,   
     
     
         2 . The interposer as in  claim 1 , wherein said at least a strip comprises strips extending peripherally around a region including an EM emission source disposed on said facing surface of said semiconductor die and said rows of solder balls are parallel. 
     
     
         3 . The interposer as in  claim 2 , wherein said EM emission source comprises an RF device, said RF device being at least one of an RF transmitter and an RF receiver. 
     
     
         4 . The interposer as in  claim 1 , wherein said rows of solder balls include three parallel rows. 
     
     
         5 . The interposer as in  claim 1 , wherein said rows of solder balls include two parallel rows and a repeating sequence of said solder balls along a longitudinal direction of said strips includes solder balls from alternating parallel rows of said two rows. 
     
     
         6 . The interposer as in  claim 1 , further comprising a further semiconductor die laterally spaced from said semiconductor die and further joined to said first surface of said interposer. 
     
     
         7 . The interposer as in  claim 1 , wherein each of said multiple rows of solder balls includes pairs of stacked solder balls arranged in said rows, each said pair interposed between said facing surface of said semiconductor die and said first surface of said interposer. 
     
     
         8 . The interposer as in  claim 1 , wherein, at each lengthwise location along a length of said strip, at least a portion of one of said solder balls is present at a location across a width of said strip. 
     
     
         9 . A semiconductor package comprising:
 a printed circuit board;   a semiconductor die; and   an interposer interposed between said printed circuit board and said semiconductor die, said interposer having first and second opposed surfaces; and   said first surface coupled to said printed circuit board and wherein a facing surface of said semiconductor die is joined to said second surface of said interposer by at least a strip of multiple rows of solder balls that extend along said facing surface on outer portions of said semiconductor die.   
     
     
         10 . The semiconductor package as in  claim 9 , wherein said multiple rows are parallel rows and further comprising a plurality of vias extending through said interposer from said first surface to said second surface and a package substrate interposed between said first surface of said interposer and said printed circuit board. 
     
     
         11 . The semiconductor package as in  claim 9 , wherein said at least a strip comprises strips extending peripherally around a region of said facing surface of said semiconductor die, each said strip including two of said rows, and wherein a repeating sequence of said solder balls along a longitudinal direction of each of said strips includes solder balls from alternating rows of said two rows. 
     
     
         12 . The semiconductor package as in  claim 11 , wherein said region includes an EM emission source. 
     
     
         13 . An interposer for connecting a semiconductor die to a printed circuit board, said interposer comprising:
 a body having opposed first and second surfaces and a plurality of conductive layers therein, said semiconductor die joined to said first surface of said interposer at a first location, said first location comprising a geometric portion of said interposer that faces said semiconductor die and wherein said interposer includes an internal electromagnetic shield in said first location, said internal electromagnetic shield being a capacitive device formed of said conductive layers.   
     
     
         14 . The interposer as in  claim 13 , wherein said plurality of conductive layers comprise metal layers and said capacitive device is a metal plate capacitor formed of overlying metal plates formed from said metal layers. 
     
     
         15 . The interposer as in  claim 13 , wherein said plurality of conductive layers comprise metal layers and said capacitive device is a metal-insulator-metal (MIM) capacitor with electrodes formed of said metal layers. 
     
     
         16 . The interposer as in  claim 13 , wherein said plurality of conductive layers includes at least one metal layer and at least one semiconductor layer and said capacitive device is a metal-oxide-semiconductor (MOS) capacitor having one capacitor plate formed of said at least one semiconductor layer and a further capacitor plate formed of said at least one metal layer. 
     
     
         17 . The interposer as in  claim 13 , wherein said plurality of conductive layers comprise metal layers and said capacitive device is a metal-oxide-metal (MOM) capacitor formed of two capacitor electrodes, each including a plurality of digital leads of at least one of said metal layers. 
     
     
         18 . The interposer as in  claim 13 , wherein said plurality of conductive layers comprise metal layers and said capacitive device is a metal-oxide-metal (MOM) capacitor formed of two capacitor electrodes formed of a first metal layer of said plurality of metal layers, a first of said two capacitor electrodes including a plurality of first parallel leads coupled together and a second of said two capacitor electrodes including a plurality of second parallel leads coupled together, said first parallel leads disposed alternatingly between adjacent ones of said second parallel leads. 
     
     
         19 . The interposer as in  claim 13 , wherein said plurality of conductive layers comprise metal layers and said capacitive device is a metal-oxide-metal (MOM) capacitor formed of two capacitor electrodes, a first of said two capacitor electrodes formed of a first metal layer of said metal layers and including a plurality of first parallel leads coupled together and a second of said two capacitor electrodes formed of a second metal layer of said metal layers and including a plurality of second parallel leads coupled together, said first and second parallel leads disposed perpendicular to one another. 
     
     
         20 . The interposer as in  claim 13 , wherein said interposer includes an electrical circuit therein and said capacitive device is a decoupling capacitor that decouples one part of said electrical circuit from another part of said electrical circuit. 
     
     
         21 . An interposer for connecting a semiconductor die to a printed circuit board, said interposer comprising:
 a substrate body having opposed first and second surfaces;   a plurality of conductive layers disposed in a dielectric material on said substrate body, wherein one of said conductive layers includes a first metal lead and a further of said conductive layers includes a second metal lead, wherein said first metal lead is shielded from said second metal lead by a shield including portions of at least one interposed conductive layer of said conductive layers;   said first metal lead extending along a longitudinal direction of said interposer and said shield extending continuously laterally across at least a majority of a transverse direction of said interposer between said first and second metal leads; and   wherein said conductive layers are formed of metal materials or semiconductor materials.   
     
     
         22 . The interposer as in  claim 21 , further comprising a plurality of vias extending through said interposer from said first surface to said second surface; and wherein each said interposed conductive layer is coupled to ground. 
     
     
         23 . The interposer as in  claim 21 , wherein said shield includes a plurality of said interposed conductive layers coupled together by conductive contacts or semiconductor contacts. 
     
     
         24 . The interposer as in  claim 21 , wherein said shield forms a continuous member of said metal materials or semiconductor materials, and there is no dielectric path from said first metal lead to said second metal lead through said shield. 
     
     
         25 . The interposer as in  claim 21 , wherein said first metal lead carries a noisy electrical signal and said second metal lead carries a further signal and said shield shields said second metal lead from electrical noise from said first metal lead. 
     
     
         26 . The interposer as in  claim 21 , wherein said first metal lead is disposed above said shield and said shield includes a width at least twenty times as wide as a width of said first metal lead. 
     
     
         27 . The interposer as in  claim 21 , wherein said shield is formed of at least first and second interposed conductive layers of said interposed conductive layers, each of said first and second interposed layers formed in a checkerboard pattern and overlaid such that said overlaid checkerboard patterns produce a solid uninterrupted pattern as viewed from above said plurality of conductive layers. 
     
     
         28 . The interposer as in  claim 27 , wherein said first and second interposed conductive layers are coupled together such that said shield is a continuous solid body. 
     
     
         29 . The interposer as in  claim 27 , wherein said first interposed conductive layer comprises metal and said second interposed conductive layer comprises polysilicon. 
     
     
         30 . An interposer for connecting a semiconductor die to a printed circuit board, said interposer comprising:
 a substrate body;   a plurality of conductive layers disposed in a dielectric material on said substrate body;   a first metal lead; and   a shield surrounding said first metal lead, said shield including at least one of semiconductor materials, portions of said conductive layers and further metal portions.   
     
     
         31 . The interposer as in  claim 30 , wherein said first metal lead extends along a longitudinal direction of said interposer and is formed of an intermediate conductive layer of said plurality of conductive layers and said shield covers opposed sides and top and bottom of said first metal lead. 
     
     
         32 . The interposer as in  claim 30 , further comprising a plurality of through-silicon-vias extending through said interposer and wherein said first metal lead carries an electrical signal and is a portion of an intermediate conductive layer of said plurality of conductive layers. 
     
     
         33 . The interposer as in  claim 32 , wherein a lower portion of said shield is a portion of a lower conductive layer of said plurality of conductive layers, an upper portion of said shield is a portion of an upper conductive layer of said plurality of conductive layers and side portions of said shield include portions of said intermediate conductive layer. 
     
     
         34 . The interposer as in  claim 33 , wherein at least one of said lower portion of said shield and said upper portion of said shield is coupled to ground. 
     
     
         35 . The interposer as in  claim 30 , wherein a further of said conductive layers includes a second metal lead that is coupled to a source of electrical noise, said second metal lead disposed outside said shield. 
     
     
         36 . The interposer as in  claim 35 , wherein said interposer is coupled to a semiconductor die and wherein said second metal lead is coupled to one of an RF receiver, an RF transmitter and an inductor formed on said semiconductor die.