Touch sensor and operating method thereof

Abstract

A touch sensor includes: a pulse signal generator for generating a pulse signal of which pulse width is calibrated in response to a control code; a pulse signal transmitter for transmitting the pulse signal when a touch object is out of contact with a touch pad and stopping transmitting the pulse signal when the touch object is in contact with the touch pad; a pulse signal detector for detecting the pulse signal transmitted through the pulse signal transmitter; and a controller recognizing a non-contact state and adjusting the control code to calibrate the pulse width of the pulse signal when the pulse signal detector detects the pulse signal. In the above-described configuration, the contact of the touch object with the touch pad can be sensed more precisely, and the occurrence of a malfunction in the touch sensor due to changed operating conditions can be prevented.

1 . A capacitance measurement circuit comprising:
 a pulse signal generator for varying a pulse width of a clock signal in response to a capacitance value, and generating a pulse signal;   a pulse signal transmitter including a pad through which a capacitance is externally received, the pulse signal transmitter being configured to or not to transmit the pulse signal in response to the capacitance applied through the pad;   a pulse signal detector for periodically detecting the pulse signal applied through the pulse signal transmitter, and outputting a detection signal;   a counter for gradually increasing or decreasing and outputting a counter value according to predetermined rules in response to the detection signal; and   a digital filter for filtering the counter value and outputting the capacitance value.   
     
     
         2 . The circuit of  claim 1 , wherein the pulse signal generator comprises:
 a clock signal generator for generating the clock signal;   a variable delay chain for variably delaying the clock signal according to the capacitance value;   an inverter for inverting and outputting the output signal of the variable delay chain; and   an AND gate for performing a logic AND on the clock signal and the output signal of the inverter, and generating the pulse signal having a pulse width corresponding to a delay time of the clock signal.   
     
     
         3 . The circuit of  claim 1 , wherein the pulse signal transmitter further comprises a resistor connected between the pulse signal generator and the pulse signal detector and configured to inhibit transmission of the pulse signal along with the capacitance applied through the pad. 
     
     
         4 . The circuit of  claim 1 , wherein the pulse signal detector comprises:
 a T-flip-flop for detecting the pulse signal in response to the clock signal, and generating an output signal that toggles in response to the pulse signal; and   a period determiner for determining whether the output signal of the T-flip-flop periodically toggles, and outputting the detection signal.   
     
     
         5 . The circuit of  claim 4 , wherein the T-flip-flop comprises:
 an SR-flip-flop for outputting the detection signal in response to the pulse signal applied to one of a set terminal and a reset terminal;   a D-flip-flop for latching and outputting the detection signal in response to the clock signal; and   a multiplexer for selecting one of the set terminal and the reset terminal in response to the output signal of the D-flip-flop, and transmitting the pulse signal to the selected terminal.   
     
     
         6 . The circuit of  claim 1 , wherein the counter gradually increases or decreases the capacitance value in response to the detection signal by a predetermined unit and outputs the capacitance value. 
     
     
         7 . The circuit of  claim 1 , wherein when the detection signal is continuously applied at a high level or low level, the counter varies the capacitance value by a variation unit of the capacitance value and gradually increases or decreases and outputs the capacitance value. 
     
     
         8 . The circuit of  claim 1 , wherein the digital filter is an LPF or BPF configured to receive and stabilize the counter value, remove a noise, and output the capacitance value. 
     
     
         9 . The circuit of  claim 1 , wherein the counter and the digital filter are embodied in software.