Determination of a status of a door lock

Abstract

A method and system for determining a status of a door lock. A receiver device receives a broadcast signal from a broadcast device built into a door. The door lock is configured to lock and unlock the door. The receiver device is located remotely from the door. The broadcast signal includes a door lock status of the door lock. The door lock status includes a first input bit of 0 or 1 and a second input bit of 0 or 1. A main receiver circuit within the receiver device uses a first AND gate and a second AND gate within the main receiver circuit to process the first input bit and the second input bit to generate a first output bit and a second output bit, respectively. The main receiver circuit stores the first and second output bits in a memory location within the receiver device.

1 . A method for remotely determining a status of a door lock, said method comprising:
 a receiver device receiving a broadcast signal from a broadcast device built into a door, said door lock configured to lock and unlock the door, said receiver device located remotely from the door, said broadcast signal comprising a door lock status of the door lock, said door lock status comprising a first input bit of 0 or 1 and a second input bit of 0 or 1;   a main receiver circuit within the receiver device using a first AND gate and a second AND gate within the main receiver circuit to process the first input bit and the second input bit to generate a first output bit and a second output bit, respectively; and   said main receiver circuit storing the first and second output bits in a memory location within the receiver device.   
     
     
         2 . The method of  claim 1 , wherein the first and second AND gates each have a first input and a second input, and wherein said using and said storing collectively comprise:
 said second input of the first AND gate receiving the first input bit;   said first AND gate performing an AND of the first input bit and a fixed input of 1 at the first input of the first AND gate to generate the first output bit;   transmitting the first output bit from an output of the first AND gate to a first field of the memory location;   said second input of the second AND gate receiving the second input bit;   said second AND gate performing an AND of the second input bit and a fixed input of 1 at the first input of the second AND gate to generate the second output bit; and   transmitting the second output bit from an output of the second AND gate to a second field of the memory location.   
     
     
         3 . The method of  claim 1 , wherein the receiver device is a key fob device configured to be attached to a key chain along with keys of a user, said key fob device having objects comprising:
 a first light which if illuminated indicates that the door is locked;   a second light which if illuminated indicates that the door is unlocked, a first button which if pressed unlocks the door, a second button which if pressed locks the door;   a third button which if pressed opens the door;   a fourth button which if pressed closes the door;   a display button which if pressed causes the door lock status in the memory location to be displayed via illumination of the first light or the second light; and   a panic bar which if pressed activates an alarm function,   wherein the method further comprises displaying the door lock status in response to the display button having been pressed.   
     
     
         4 . The method of  claim 1 , wherein the receiver device is a key fob device comprising a display button which if pressed causes the door lock status in the memory location to be displayed, and wherein the method further comprises:
 in response to the display button having been pressed, a display circuit processing the first and second output bits in the memory location to display the door lock status, wherein the receiver device comprises the display circuit.   
     
     
         5 . The method of  claim 4 , wherein the display circuit comprises a third AND gate, a fourth AND gate, a first pass transistor, a second pass transistor, a first light and a second light, wherein the third AND gate comprises a first input having a fixed value of 1, a second input, and an output coupled to an input of the first pass transistor, wherein the fourth AND gate comprises a first input having the fixed value of 1, a second input, and an output coupled to an input of the second pass transistor, wherein an output of the first pass transistor is coupled to an input of the first light, wherein an output of the second pass transistor is coupled to an input of the second light, and wherein said processing comprises:
 said second input of the third AND gate and said second input of the fourth AND gate receiving the first output bit and the second output bit from a first field and a second field of the memory location, respectively;   said third AND gate performing an AND of the received first output bit and the fixed value of  1  at the first input of the third AND gate to generate a third output bit;   transmitting the third output bit from the output of the third AND gate to the input of the first pass transistor to trigger or prevent illumination of the first light if the third output bit is 1 or 0, respectively;   said fourth AND gate performing an AND of the received second output bit and the fixed value of 1 at the first input of the fourth AND gate to generate a fourth output bit; and   transmitting the fourth output bit from the output of the fourth AND gate to the input of the second pass transistor to trigger or prevent illumination of the second light if the fourth output bit is 1 or 0, respectively.   
     
     
         6 . The method of  claim 5 ,
 wherein said to trigger or prevent illumination of the first light comprises: (i) to cause, if the third output bit is 1, the output of the first pass transistor to open which triggers illumination of the first light and (ii) to cause, if the third output bit is 0, the output of the first pass transistor to close to which prevents illumination of the first light; and   wherein to trigger or prevent illumination of the second light comprises: (i) to cause, if the fourth output bit is 1, the output of the second pass transistor to open to which triggers illumination of the second light and (ii) to cause, if the fourth output bit is 0, the output of the second pass transistor to close which prevents illumination of the second light.   
     
     
         7 . A computer program product, comprising a computer readable physically tangible storage medium having computer readable instructions stored therein, said instructions configured to be executed by a receiver device to implement a method for remotely determining a status of a door lock, said method comprising:
 said receiver device receiving a broadcast signal from a broadcast device built into a door, said door lock configured to lock and unlock the door, said receiver device located remotely from the door, said broadcast signal comprising a door lock status of the door lock, said door lock status comprising a first input bit of 0 or 1 and a second input bit of 0 or 1;   a main receiver circuit within the receiver device using a first AND gate and a second AND gate within the main receiver circuit to process the first input bit and the second input bit to generate a first output bit and a second output bit, respectively; and   said main receiver circuit storing the first and second output bits in a memory location within the receiver device.   
     
     
         8 . The method of  claim 7 , wherein the first and second AND gates each have a first input and a second input, and wherein said using and said storing collectively comprise:
 said second input of the first AND gate receiving the first input bit;   said first AND gate performing an AND of the first input bit and a fixed input of 1 at the first input of the first AND gate to generate the first output bit;   transmitting the first output bit from an output of the first AND gate to a first field of the memory location;   said second input of the second AND gate receiving the second input bit;   said second AND gate performing an AND of the second input bit and a fixed input of 1 at the first input of the second AND gate to generate the second output bit; and   transmitting the second output bit from an output of the second AND gate to a second field of the memory location.   
     
     
         9 . The computer program product of  claim 7 , wherein the receiver device is a key fob device configured to be attached to a key chain along with keys of a user, said key fob device having objects comprising a first light which if illuminated indicates that the door is locked, a second light which if illuminated indicates that the door is unlocked, a first button which if pressed unlocks the door, a second button which if pressed locks the door, a third button which if pressed opens the door, a fourth button which if pressed closes the door, a display button which if pressed causes the door lock status in the memory location to be displayed via illumination of the first light or the second light, and a panic bar which if pressed activates an alarm function, and wherein the method further comprises displaying the door lock status in response to the display button having been pressed. 
     
     
         10 . The computer program product of  claim 7 , wherein the receiver device is a key fob device comprising a display button which if pressed causes the door lock status in the memory location to be displayed, and wherein the method further comprises:
 in response to the display button having been pressed, a display circuit processing the first and second output bits in the memory location to display the door lock status, wherein the receiver device comprises the display circuit.   
     
     
         11 . The computer program product of  claim 10 , wherein the display circuit comprises a third AND gate, a fourth AND gate, a first pass transistor, a second pass transistor, a first light and a second light, wherein the third AND gate comprises a first input having a fixed value of 1, a second input, and an output coupled to an input of the first pass transistor, wherein the fourth AND gate comprises a first input having the fixed value of 1, a second input, and an output coupled to an input of the second pass transistor, wherein an output of the first pass transistor is coupled to an input of the first light, wherein an output of the second pass transistor is coupled to an input of the second light, and wherein said processing comprises:
 said second input of the third AND gate and said second input of the fourth AND gate receiving the first output bit and the second output bit from a first field and a second field of the memory location, respectively;   said third AND gate performing an AND of the received first output bit and the fixed value of 1 at the first input of the third AND gate to generate a third output bit;   transmitting the third output bit from the output of the third AND gate to the input of the first pass transistor to trigger or prevent illumination of the first light if the third output bit is 1 or 0, respectively;   said fourth AND gate performing an AND of the received second output bit and the fixed value of 1 at the first input of the fourth AND gate to generate a fourth output bit; and   transmitting the fourth output bit from the output of the fourth AND gate to the input of the second pass transistor to trigger or prevent illumination of the second light if the fourth output bit is 1 or 0, respectively.   
     
     
         12 . The computer program product of  claim 11 ,
 wherein said to trigger or prevent illumination of the first light comprises: (i) to cause, if the third output bit is 1, the output of the first pass transistor to open which triggers illumination of the first light and (ii) to cause, if the third output bit is 0, the output of the first pass transistor to close to which prevents illumination of the first light; and   wherein to trigger or prevent illumination of the second light comprises: (i) to cause, if the fourth output bit is 1, the output of the second pass transistor to open to which triggers illumination of the second light and (ii) to cause, if the fourth output bit is 0, the output of the second pass transistor to close which prevents illumination of the second light.   
     
     
         13 . A system for remotely determining a status of a door lock, said system comprising:
 a receiver device configured to receive a broadcast signal from a broadcast device built into a door, said door lock configured to lock and unlock the door, said receiver device located remotely from the door, said broadcast signal comprising a door lock status of the door lock, said door lock status comprising a first input bit of 0 or 1 and a second input bit of 0 or 1;   a main receiver circuit within the receiver device, said main receiver circuit configured to use a first AND gate and a second AND gate within the main receiver circuit to process the first input bit and the second input bit to generate a first output bit and a second output bit, respectively,   wherein the main receiver circuit is configured to store the first and second output bits in a memory location within the receiver device.   
     
     
         14 . The system of  claim 13 , wherein the first and second AND gates each have a first input and a second input, and wherein said to use and said to process collectively comprise:
 to receive, by second input of the first AND gate, the first input bit;   to perform, by the first AND gate, an AND of the first input bit and a fixed input of 1 at the first input of the first AND gate to generate the first output bit;   to transmit the first output bit from an output of the first AND gate to a first field of the memory location;   to receive, by the second input of the second AND gate, the second input bit;   to perform, by the second AND gate, an AND of the second input bit and a fixed input of 1 at the first input of the second AND gate to generate the second output bit; and   to transmit the second output bit from an output of the second AND gate to a second field of the memory location.   
     
     
         15 . The system of  claim 13 , wherein the receiver device is a key fob device configured to be attached to a key chain along with keys of a user, said key fob device having objects comprising:
 a first light which if illuminated indicates that the door is locked, a second light which if illuminated indicates that the door is unlocked;   a first button which if pressed unlocks the door;   a second button which if pressed locks the door;   a third button which if pressed opens the door;   a fourth button which if pressed closes the door;   a display button which if pressed causes the door lock status in the memory location to be displayed via illumination of the first light or the second light; and   a panic bar which if pressed activates an alarm function,   wherein the system further comprises means for displaying the door lock status in response to the display button having been pressed.   
     
     
         16 . The system of  claim 13 , wherein the receiver device is a key fob device comprising a display button which if pressed causes the door lock status in the memory location to be displayed, and wherein the system further comprises:
 a display circuit configured to process, in response to the display button having been pressed, the first and second output bits in the memory location to display the door lock status, wherein the receiver device comprises the display circuit.   
     
     
         17 . The system of  claim 16 , wherein the display circuit comprises a third AND gate, a fourth AND gate, a first pass transistor, a second pass transistor, a first light and a second light, wherein the third AND gate comprises a first input having a fixed value of  1 , a second input, and an output coupled to an input of the first pass transistor, wherein the fourth AND gate comprises a first input having the fixed value of 1, a second input, and an output coupled to an input of the second pass transistor, wherein an output of the first pass transistor is coupled to an input of the first light, wherein an output of the second pass transistor is coupled to an input of the second light, and wherein said to process comprises:
 to receive, by the second input of the third AND gate and the second input of the fourth AND gate, the first output bit and the second output bit from a first field and a second field of the memory location, respectively;   to perform, by the third AND gate, an AND of the received first output bit and the fixed value of 1 at the first input of the third AND gate to generate a third output bit;   to transmit the third output bit from the output of the third AND gate to the input of the first pass transistor to trigger or prevent illumination of the first light if the third output bit is 1 or 0, respectively;   to perform, by the fourth AND gate, an AND of the received second output bit and the fixed value of 1 at the first input of the fourth AND gate to generate a fourth output bit; and   to transmit the fourth output bit from the output of the fourth AND gate to the input of the second pass transistor to trigger or prevent illumination of the second light if the fourth output bit is 1 or 0, respectively.   
     
     
         18 . The system of  claim 17 ,
 wherein said to trigger or prevent illumination of the first light comprises: (i) to cause, if the third output bit is 1, the output of the first pass transistor to open which triggers illumination of the first light and (ii) to cause, if the third output bit is 0, the output of the first pass transistor to close to which prevents illumination of the first light; and   wherein to trigger or prevent illumination of the second light comprises: (i) to cause, if the fourth output bit is 1, the output of the second pass transistor to open to which triggers illumination of the second light and (ii) to cause, if the fourth output bit is 0, the output of the second pass transistor to close which prevents illumination of the second light.