Data processing apparatus address range dependent parallelization of instructions

Abstract

A data processing apparatus has an instruction memory system arranged to output an instruction word addressed by an instruction address. An instruction execution unit, processes a plurality of instructions from the instruction word in parallel. A detection unit, detects in which of a plurality of ranges the instruction address lies. The detection unit is coupled to the instruction execution unit and/or the instruction memory system, to control a way in which the instruction execution unit parallelizes processing of the instructions from the instruction word, dependent on a detected range. In an embodiment the instruction execution unit and/or the instruction memory system adjusts a width of the instruction word that determines a number of instructions from the instruction word that is processed in parallel, dependent on the detected range.

1 - 17 . (canceled) 
     
     
         18 . An apparatus, comprising:
 an instruction memory system configured to output an instruction word addressed by an instruction address, wherein the instruction memory system includes a first memory unit configured to store instruction words and a second memory unit slower than the first memory unit and configured to store smaller instruction words than the instruction words of the first memory unit;   an instruction execution unit configured to process a plurality of instructions from the instruction word during a period of time; and   a detection unit configured to cause the instruction execution unit to process multiple of the plurality of instructions during the time period from the instruction word responsive to detection of whether the instruction address corresponds to the first memory unit or the second memory unit.   
     
     
         19 . The apparatus of  claim 18 , wherein the instruction memory system is configured to adjust a width of the instruction word responsive to detection of whether the instruction address corresponds to the first memory unit or the second memory unit. 
     
     
         20 . The apparatus of  claim 18 , wherein the instruction memory system is configured to adjust a quantity of instructions comprising the instruction word responsive to detection of whether the instruction address corresponds to the first memory unit or the second memory unit. 
     
     
         21 . The apparatus of  claim 18 , wherein:
 the instruction execution unit comprises a plurality of functional units; and   the instruction execution unit is configured to select a first set of functional units from the plurality of functional units to execute the plurality of instructions in response to detecting that the instruction address corresponds to the first memory unit.   
     
     
         22 . The apparatus of  claim 21 , wherein the instruction execution unit is further configured to select a second set of functional units from the plurality of functional units to execute the plurality of instructions in response to detecting that the instruction address corresponds to the second memory unit. 
     
     
         23 . The apparatus of  claim 22 , wherein the first set of functional units comprises one or more functional units from the second set of functional units. 
     
     
         24 . The apparatus of  claim 18 , wherein the instruction memory system is configured to disable a clock signal to the first memory unit in response to the instruction address corresponding to the second memory unit. 
     
     
         25 . The apparatus of  claim 18 , wherein the instruction memory system is configured to disable a clock signal to the second memory unit in response to the instruction address corresponding to the first memory unit. 
     
     
         26 . The apparatus of  claim 18 , wherein one or more groups of functional units from the plurality of functional units are dedicated to execution of instructions from the first memory unit. 
     
     
         27 . The apparatus of  claim 26 , wherein the instruction execution unit is further configured to disable a clock signal to the one or more groups of functional units in response to detecting that the instruction address corresponds to the second memory unit. 
     
     
         28 . A method, comprising:
 detecting, based on an instruction address, whether an instruction word is stored in a first memory unit or a second memory unit that is slower than the first memory unit and that is configured to store smaller instruction words than the instruction words of the first memory unit; and   processing a plurality instructions of the instruction word, wherein said processing comprises executing, responsive to said detecting, multiple instructions of the plurality of instructions such that at least portions of the multiple instructions are executed concurrently.   
     
     
         29 . The method of  claim 28 , further comprising adjusting a width of the instruction word responsive to said detecting. 
     
     
         30 . The method of  claim 28 , further comprising adjusting a quantity of instructions comprising the instruction word responsive to said detecting. 
     
     
         31 . The method of  claim 28 , wherein said processing comprises:
 selecting a first set of functional units from a plurality of functional units to execute the plurality of instructions in response to detecting that the instruction address corresponds to the first memory unit; and   selecting a second set of functional units from the plurality of functional units to execute the plurality of instructions in response to detecting that the instruction address corresponds to the second memory unit.   
     
     
         32 . The method of  claim 28 , further comprising disabling a clock signal to the first memory unit in response to detecting that the instruction address corresponds to the second memory unit. 
     
     
         33 . The method of  claim 28 , further comprising disabling a clock signal to one or more groups of functional units dedicated to the first memory unit in response to detecting that the instruction address corresponds to the second memory unit. 
     
     
         34 . A computer-readable storage medium comprising a plurality of instructions, that in response to being executed, cause an apparatus to:
 load instructions for an inner loop of a program in a first memory unit configured to store longer instruction words;   load other instructions of the program in a second memory unit that is slower than the first memory unit and that is configured to store smaller instruction words; and   parallelize execution of instructions from instruction words in the first memory unit and the second memory unit responsive to whether an instruction word is from the first memory unit or the second memory unit.   
     
     
         35 . The computer-readable storage medium of  claim 34 , wherein the plurality of instructions, in response to being executed, further cause the apparatus to adjust a quantity of instructions comprising the instruction word being executed responsive to whether an instruction address for the instruction word corresponds to the first memory unit or the second memory unit. 
     
     
         36 . The computer-readable storage medium of  claim 35 , wherein the plurality of instructions, in response to being executed, further cause the apparatus to disable a clock signal to the first memory unit in response to detecting that the instruction address corresponds to the second memory unit. 
     
     
         37 . The computer-readable storage medium of  claim 35 , wherein the plurality of instructions, in response to being executed, further cause the apparatus to disable a clock signal to one or more groups of functional units dedicated to the first memory unit in response to detecting that the instruction address corresponds to the second memory unit.