Turbo decoder metrics initialization

Abstract

Disclosed are various embodiments that provide turbo decoding implemented as at least a portion of baseband processing circuitry. A turbo decoder may obtain a data block associated with a transmission time interval, the data block comprising a sequence of bits, the data block being encoded according to a coding rate. An alpha operation is performed on the data block for a first decoding iteration to generate first alpha decode data, the alpha operation for the first decoding iteration being performed continuously. An alpha operation is performed on the data block for a second decoding iteration to generate second alpha decode data, the alpha operation for the second decoding iteration being performed according to a set of alpha evaluation windows. The initialization of the alpha windows during the second alpha decode may be derived from the alpha state data that is stored in memory from the first alpha decode.

Therefore, at least the following is claimed: 
     
         1 . A method comprising:
 obtaining a data block associated with a transmission time interval, the data block comprising a sequence of bits, the data block being encoded according to a coding rate;   performing on the data block an alpha operation for a first decoding iteration to generate first alpha decode data, the alpha operation for the first decoding iteration being performed continuously; and   performing on the data block an alpha operation for a second decoding iteration to generate second alpha decode data, the alpha operation for the second decoding iteration being performed according to a set of alpha evaluation windows.   
     
     
         2 . The method of  claim 1 , wherein the alpha operation for the second decoding iteration comprises ordering the set of alpha evaluation windows according to a direction that is reversed with respect to the sequence of bits. 
     
     
         3 . The method of  claim 1 , wherein each evaluation window in the set of alpha evaluation windows corresponds to a respective start position. 
     
     
         4 . The method of  claim 3 , wherein performing the alpha operation for the first decoding iteration comprises storing an alpha state values for each respective start position, wherein each evaluation window corresponds to an alpha state value. 
     
     
         5 . The method of  claim 4 , wherein performing the alpha operation for the second decoding iteration comprises initializing each evaluation window according to the corresponding alpha state value. 
     
     
         6 . The method of  claim 1 , further comprising:
 performing on the data block a beta operation for the first decoding iteration to generate first beta decode data, the beta operation for the first decoding iteration being performed according to a set of beta evaluation windows.   
     
     
         7 . The method of  claim 6 , wherein the beta operation for the first decoding iteration comprises ordering the set of beta evaluation windows according to a direction correlating with the sequence of bits. 
     
     
         8 . A system comprising:
 a memory buffer configured to store a data block associated with a transmission time interval; and   a turbo decoder module in data communication with the memory buffer, the turbo decoder module being configured to:
 perform complete decode operations on the data block for a predetermined number of iterations, each complete decode operation comprising performing an alpha operation and a beta operation; 
 continuously perform the beta operation for a first iteration; 
 discontinuously perform the beta operation for a second iteration according to a set of beta evaluation windows; and 
 generate likelihood data based at least upon performing a combination of the alpha operations and the beta operations. 
   
     
     
         9 . The system of  claim 8 , wherein the turbo decoder module is further configured to store beta state values calculated from the first iteration. 
     
     
         10 . The system of  claim 9 , wherein each beta state value corresponds to a start position associated with each beta evaluation window of the second iteration, wherein the turbo decoder module is further configured to initialize each beta evaluation window according to the corresponding beta state value. 
     
     
         11 . The system of  claim 9 , wherein each beta evaluation window excludes a preceding training window configured to initializing the beta evaluation window. 
     
     
         12 . The system of  claim 8 , wherein the turbo decoder module is further configured to discontinuously perform the alpha operation for the first iteration according to a set of alpha evaluation windows. 
     
     
         13 . The system of  claim 12 , wherein the turbo decoder module is further configured to continuously perform the alpha operation for the second iteration. 
     
     
         14 . The system of  claim 12 , wherein each alpha evaluation window of the first iteration is configured to be initialized according to a default state value. 
     
     
         15 . A system comprising:
 processing circuitry configured to:
 obtain a data block associated with a transmission time interval, the data block comprising a sequence of bits; 
 perform on the data block an un-windowed alpha operation for a first decoding iteration; 
 perform on the data block a beta operation for the first decoding iteration according to a set of beta evaluation windows of the first decoding iteration; 
 perform on the data block an un-windowed beta operation for a second decoding iteration; and 
 generate log likelihood data based at least upon the un-windowed alpha operation for the first decoding iteration and the beta operation for the first decoding iteration. 
   
     
     
         16 . The system of  claim 15 , wherein the processing circuitry is further configured to perform on the data block an alpha operation for the second decoding iteration according to a set of alpha evaluation windows of the second decoding iteration. 
     
     
         17 . The system of  claim 16 , wherein the processing circuitry is further configured to initialize each alpha evaluation window according to state value data generated from the un-windowed alpha operation for the first decoding iteration. 
     
     
         18 . The system of  claim 15 , wherein the processing circuitry is further configured to:
 perform on the data block a beta operation for a third decoding iteration according to a set of beta evaluation windows of the third decoding iteration; and   initialize each beta evaluation window for the third decoding iteration according to state value data generated from the un-windowed beta operation for the second decoding iteration.   
     
     
         19 . The system of  claim 18 , wherein the processing circuitry is further configured to initialize each beta evaluation window for the first decoding iteration according to a default state value. 
     
     
         20 . The system of  claim 15 , wherein each beta evaluation window excludes a preceding training window configured to initializing the beta evaluation window.