Light emitting diode chip, light emitting diode package structure, and method for forming the same

Abstract

A light emitting diode chip, a light emitting diode package structure and a method for forming the same are provided. The light emitting diode chip includes a bonding layer, which has a plurality of voids, or a minimum horizontal distance between a surrounding boundary of the light emitting diode chip and the bonding layer is larger than O. The light emitting diode chip, the light emitting diode package structure and the method may improve the product yields and enhance the light emitting efficiency.

What is claimed is: 
     
         1 . A method for forming a light emitting diode, comprising:
 providing a substrate having a first semiconductor layer, a light emitting layer and a second semiconductor layer formed thereon sequentially;   performing a patterning process to the first semiconductor layer, the light emitting layer and the second semiconductor layer to define a plurality of protruded portions and a plurality of depressed portions, wherein a remaining portion of the first semiconductor layer covers the substrate in the depressed portions;   forming a plurality of first electrodes on the first semiconductor layer in the depressed portions;   forming a plurality of second electrodes on the second semiconductor layer in the protruded portions;   cutting the substrate along a scribe line located on the depressed portion, for separating a plurality of light emitting diode chips, wherein the light emitting diode chip has a bonding layer and a remained substrate portion, wherein the bonding layer has a plurality of voids, or a minimum horizontal distant between a surrounding boundary of the light emitting diode chip and the bonding layer is larger than 0;   bonding the light emitting diode chip with a carrier substrate via the bonding layer;   forming a surrounding layer on the carrier substrate to surround the light emitting diode;   removing the remained substrate portion to form a cavity; and   filling a wavelength conversion layer into the cavity.   
     
     
         2 . A light emitting diode chip, comprising:
 a substrate having a boundary;   a first semiconductor layer disposed on the substrate;   a light emitting layer disposed on the first semiconductor layer; and   a second semiconductor layer disposed on the light emitting layer,   wherein the light emitting diode chip is characterized by only one electrode disposed on the second semiconductor layer, and the electrode and the boundary has a minimum horizontal distance therebetween of at least about 10 μm.   
     
     
         3 . The light emitting diode chip of  claim 2 , wherein the minimum horizontal distance is at least about 20 μm. 
     
     
         4 . The light emitting diode chip of  claim 2 , wherein the electrode is disposed on the second semiconductor layer and exposes a portion of the second semiconductor layer. 
     
     
         5 . The light emitting diode chip of  claim 4 , wherein the electrode is disposed on the second semiconductor layer and exposes a portion of the upper surface of the second semiconductor layer. 
     
     
         6 . The light emitting diode chip of  claim 5 , further comprising a passivation layer disposed on the second semiconductor layer and covers the exposed upper surface of the second semiconductor layer. 
     
     
         7 . The light emitting diode chip of  claim 2 , further comprising a passivation layer disposed on the second semiconductor layer and extends to the sidewalls f the sidewalls of the second semiconductor layer, the sidewalls of the light emitting layer and the sidewalls of the protruded portion of the first semiconductor layer, wherein the electrode is disposed on the passivation layer. 
     
     
         8 . The light emitting diode chip of  claim 2 , further comprising a patterned passivation layer disposed between the second semiconductor layer and the electrode, wherein a portion of the electrode directly contacts the second semiconductor layer. 
     
     
         9 . The light emitting diode chip of  claim 2 , wherein the light emitting diode chip has tapered sidewalls. 
     
     
         10 . A light emitting diode packaging structure, comprising:
 a light emitting diode chip as claimed in  claim 2 ; and   a carrier substrate, wherein the light emitting diode chip is disposed on the carrier substrate.   
     
     
         11 . A light emitting diode chip, comprising:
 a substrate, having a surrounding boundary;   a first semiconductor layer, a light emitting layer, and a second semiconductor layer subsequently disposed on the substrate; and   electrode islands disposed on the second semiconductor layer.   
     
     
         12 . The light emitting diode chip as claimed in  claim 11 , wherein the ratio between the total area of a top surface of the electrode islands and the area of a top surface of the substrate is equal to or less than 95%. 
     
     
         13 . The light emitting diode chip as claimed in  claim 11 , wherein the electrode island has a thickness which is equal to or more than 1 μm. 
     
     
         14 . The light emitting diode chip as claimed in  claim 11 , further comprising:
 a passivation layer disposed on a side wall of the first semiconductor layer, and a side wall of the light emitting layer.   
     
     
         15 . The light emitting diode chip as claimed in  claim 14 , wherein the passivation layer further extends to a side wall of the second semiconductor layer. 
     
     
         16 . The light emitting diode chip as claimed in  claim 15 , wherein the passivation layer further extends to a side wall of a part of the electrode islands. 
     
     
         17 . The light emitting diode chip as claimed in  claim 11 , wherein the electrode island has a cross-section profile in the shape of a semicircle, a polygon; or combinations thereof. 
     
     
         18 . The light emitting diode chip as claimed in  claim 11 , wherein the light emitting diode chip has taper side walls toward the substrate. 
     
     
         19 . A light emitting diode package structure, comprising:
 a light emitting diode chip having a surrounding boundary;   a carrier substrate; and   a bonding layer for bonding the light emitting diode chip with the carrier substrate, wherein the bonding layer has a plurality of voids,   wherein the light emitting diode chip comprises:   a substrate, having the surrounding boundary; and   a first semiconductor layer, a light emitting layer, and a second semiconductor layer subsequently disposed on the substrate, wherein the first semiconductor layer directly contacts to the bonding layer.   
     
     
         20 . The light emitting diode package structure as claimed in  claim 19 , wherein the bonding layer comprises:
 a first bonding layer, directly contacting the carrier substrate; and   a second bonding layer, directly contacting the second semiconductor layer, wherein at least one of the first bonding layer and the second bonding layer has island structure.   
     
     
         21 . The light emitting diode package structure as claimed in  claim 20 , wherein a minimum horizontal distant between the surrounding boundary and the at least one of the first bonding layer and the second bonding layer is larger than 0. 
     
     
         22 . The light emitting diode package structure as claimed in  claim 19 , further comprising:
 a passivation layer disposed on a side wall of the first semiconductor layer, and a side wall of the light emitting layer.   
     
     
         23 . The light emitting diode package structure as claimed in  claim 19 , wherein the light emitting diode chip further comprises an electrode, disposed on the substrate, opposite to the first semiconductor layer. 
     
     
         24 . The light emitting diode package structure as claimed in  claim 23 , wherein there is no opaque wire disposed on the electrode. 
     
     
         25 . A light emitting diode package structure, comprising:
 a light emitting diode chip having a surrounding boundary;   a carrier substrate; and   a bonding layer for bonding the light emitting diode chip with the carrier substrate, wherein the bonding layer has a plurality of voids,   wherein the light emitting diode chip comprises:   a first semiconductor layer; and   a light emitting layer, and a second semiconductor layer subsequently disposed on the first semiconductor layer, wherein the first semiconductor layer directly contacts to the bonding layer.   
     
     
         26 . A light emitting diode structure, comprising:
 a submount having a first surface and a second surface opposite the first surface;   a stacked structure comprising a first semiconductor layer, an active layer, and a second semiconductor layer laminated on the first surface;   a first electrode disposed apart from the stacked structure on the first surface;   an isolation layer disposed on the first surface, wherein the isolation layer surrounds the stacked structure and covers the lateral sides of the active layer; and   a conductive thin film layer for connecting the first electrode to the stacked structure, wherein the conductive thin film layer covers the stacked structure.   
     
     
         27 . The light emitting diode structure as claimed in  claim 26 , further comprising:
 an electrostatic discharge protection element disposed under the first electrode and embedded in the submount.   
     
     
         28 . The light emitting diode structure as claimed in  claim 26 , further comprising:
 a second electrode disposed on the second surface of the submount.   
     
     
         29 . The light emitting diode structure as claimed in  claim 26 , wherein the first electrode is disposed along all the lateral sides of the active layer. 
     
     
         30 . The light emitting diode structure as claimed in  claim 26 , wherein the first electrode is disposed along three of the lateral sides of the stacked structure. 
     
     
         31 . The light emitting diode structure as claimed in  claim 26 , wherein the submount further comprises a cavity on the first surface for receiving the stacked structure. 
     
     
         32 . The light emitting diode structure as claimed in  claim 31 , further comprising:
 a phosphor filling the cavity and covering the stacked structure.   
     
     
         33 . The light emitting diode structure as claimed in  claim 26 , wherein the conductive thin film layer comprises a plurality of openings corresponding to the stacked structure. 
     
     
         34 . The light emitting diode structure as claimed in  claim 26 , wherein the conductive thin film layer comprises a light extracting feature corresponding to the stacked structure. 
     
     
         35 . The light emitting diode structure as claimed in  claim 26 , wherein the light transmittance of the conductive thin film layer for a primary wavelength of the light generated by the active layer is greater than 60%. 
     
     
         36 . The light emitting diode structure as claimed in  claim 26 , further comprising:
 a second electrode disposed apart from the stacked structure on the first surface of the submount.   
     
     
         37 . The light emitting diode structure as claimed in  claim 26 , further comprising:
 an auxiliary electrode disposed on the conductive thin film layer for connecting the first electrode to the stacked structure, wherein the auxiliary electrode covers a part of the conductive thin film layer.   
     
     
         38 . A light emitting diode packaging structure, comprising:
 a packaging substrate;   at least one stacked structure disposed on the packaging substrate, wherein the at least one stacked structure comprises a first semiconductor layer, an active layer and a second semiconductor layer laminated on a first surface of the packaging substrate;   at least one first electrode disposed apart from the at least one stacked structure on the first surface;   at least one second electrode disposed on the packaging substrate and electrically connected the at least one stacked structure;   an isolation layer disposed on the first surface, wherein the isolation layer surrounds the at least one stacked structure and covers the lateral sides of the active layer;   at least one conductive thin film layer for connecting the at least one first electrode to the at least one stacked structure, wherein the at least one conductive thin film layer covers the at least one stacked structure; and   a transparent sealant covering the at least one conductive thin film layer.   
     
     
         39 . The light emitting diode packaging structure as claimed in  claim 38 , wherein the packaging substrate is a semiconductor substrate, and the light emitting diode packaging structure further comprises:
 at least one electrostatic discharge protection element disposed under the at least one first electrode and embedded in the packaging substrate.   
     
     
         40 . The light emitting diode packaging structure as claimed in  claim 38 , wherein the second electrode is disposed between the packaging substrate and the stacked structure. 
     
     
         41 . The light emitting diode packaging structure as claimed in  claim 38 , wherein the at least one first electrode is disposed along all the lateral sides of the active layer. 
     
     
         42 . The light emitting diode packaging structure as claimed in  claim 38 , wherein the at least one first electrode is disposed along three of the lateral sides of the at least one stacked structure. 
     
     
         43 . The light emitting diode packaging structure as claimed in  claim 38 , further comprising:
 an interface layer disposed between the least one stacked structure and the packaging substrate.   
     
     
         44 . The light emitting diode packaging structure as claimed in  claim 38 , wherein the at least one conductive thin film layer comprises a plurality of openings corresponding to the at least one stacked structure. 
     
     
         45 . The light emitting diode packaging structure as claimed in  claim 38 , wherein the at least one conductive thin film layer comprises a light extracting feature corresponding to the at least one stacked structure. 
     
     
         46 . The light emitting diode packaging structure as claimed in  claim 38 , wherein the light transparence of the at least one conductive thin film layer for a primary wavelength of the light generated by the active layer is greater than 60%. 
     
     
         47 . The light emitting diode packaging structure as claimed in  claim 38 , further comprising:
 at least one auxiliary electrode disposed on the at least one conductive thin film layer for connecting the at least one first electrode to the at least one stacked structure, wherein the at least one auxiliary electrode covers a part of the at least one conductive thin film layer.   
     
     
         48 . The light emitting diode packaging structure as claimed in  claim 38 , wherein the packaging substrate comprises two through holes extending from the first surface to a second surface opposite the first surface, and the two through holes correspond to the first electrode and the second electrode respectively. 
     
     
         49 . A light emitting diode structure, comprising:
 a substrate with a light emitting semiconductor stacked layer formed thereon;   a surrounding layer located on the substrate to surround the light emitting semiconductor stacked layer, constituting a cavity; and   a wavelength conversion layer filled into the cavity.   
     
     
         50 . The light emitting diode structure as claimed in  claim 49 , wherein the wavelength conversion layer further comprises a filler. 
     
     
         51 . A method for fabricating a light emitting diode structure, comprising:
 providing a light emitting diode having a bonding material, a stacked layer and a substrate;   bonding the light emitting diode on a carrier via the bonding material;   forming a surrounding layer to surround the light emitting diode;   removing the substrate to form a cavity; and   filling a wavelength conversion layer into the cavity.   
     
     
         52 . The method as claimed in  claim 51 , further comprising:
 performing a planarization process to the surrounding layer and the wavelength conversion layer, forcing a top surface of the wavelength conversion layer being perpendicular to sidewalls of the surrounding layer.