Semiconductor memory device having open bit line structure

Abstract

A semiconductor memory device has an array structure of an open bit line structure and comprises a plurality of normal memory mats, two dummy mats and a plurality of rows of sense amplifiers. The normal memory mat includes a plurality of memory cells and arranged in a bit line extending direction, while the dummy mat includes a plurality of dummy cells and arranged in a bit line extending direction at both ends of the plurality of normal memory mats. The rows of sense amplifiers are arranged between the normal memory mats and between each of the normal memory mats and each of the dummy mats. A first predetermined number of the dummy cells, the number of which is smaller than a number of the memory cells arranged along each bit line of the normal memory mats, are arranged along each bit line of the dummy mats.

1 - 19 . (canceled) 
     
     
         20 . A semiconductor device comprising:
 a plurality of sense amplifiers each including first and second nodes and configured to amplify, when activated, a potential difference between the first and second nodes, the sense amplifiers being arranged to include a first end sense amplifier, a second end sense amplifier and at least one intermediate sense amplifier between the first and second end sense amplifiers;   a plurality of bit lines including first, second, third and fourth bit lines, the first bit line being in electrical contact with the first node of the first end sense amplifier and extending therefrom toward the intermediate sense amplifier, the second bit line being in electrical contact with the first node of the second end sense amplifier and extending therefrom toward the intermediate sense amplifier, the third bit line being in electrical contact with the first node of the intermediate sense amplifier and extending therefrom toward the first end sense amplifier, and the fourth bit line being in electrical contact with the second node of the intermediate sense amplifier and extending therefrom toward the second end sense amplifier;   a plurality of memory cells including first memory cells, second memory cells, third memory cells, and fourth memory cells, each of the first memory cells being coupled to the first bit line, each of the second memory cells being coupled to the second bit line, each of the third memory cells being coupled to the third bit line, and each of the fourth memory cells being coupled to the fourth bit line;   a first end bit line extending from the second node of the first end sense amplifier in electrical contact therewith toward an opposite side to the intermediate sense amplifier, the first end bit line being shorter than the first bit line;   a second end bit line extending from the second node of the second end sense amplifier in electrical contact therewith toward an opposite side to the intermediate sense amplifier, the second end bit line being shorter than the second bit line;   at least one first capacitor configured to be connected to the first end bit line at least when one of the first memory cells is selected, the first end bit line being increased in capacitance by the first capacitor at least when one of the first memory cells is selected; and   at least one second capacitor configured to be connected to the second end bit line at least when one of the second memory cells is selected, the second end bit line being increased in capacitance by the second capacitor at least when one of the second memory cells is selected.   
     
     
         21 . The device as claimed in  claim 20 , further comprising at least one third capacitor and at least one fourth capacitor, the third capacitor being configured to be connected to the first end bit line at least when one of the first memory cells is selected, the first end bit line being further increased in capacitance by the third capacitor at least when one of the first memory cells is selected, and the fourth capacitor being configured to be connected to the second end bit line at least when one of the second memory cells is selected, the second end bit line being further increased in capacitance by the fourth capacitor at least when one of the second memory cells is selected. 
     
     
         22 . The device as claimed in  claim 20 , wherein each of the first, second, third and fourth memory cells being selected by changing of an associate one of word lines from an inactive level to an active level, the first capacitor being configured to be connected to the first end bit line approximately simultaneously with a change of an associated word line from the inactive level to the active level, and the second capacitor being configured to be connected to the first end bit line approximately simultaneously with a change of an associated word line from the inactive level to the active level. 
     
     
         23 . The device as claimed in  claim 20 , wherein each of the first, second, third and fourth memory cells being selected by changing of an associate one of word lines from an inactive level to an active level, the first capacitor being configured to be connected to the first end bit line prior to a change of an associated word line from the inactive level to the active level, and the second capacitor being configured to be connected to the first end bit line prior to a change of an associated word line from the inactive level to the active level. 
     
     
         24 . The device as claimed in  claim 20 , wherein each of the first, second, third and fourth memory cells comprises a DRAM cell including a cell transistor and a cell capacitor, each of the first and second capacitors being greater in capacitance than the cell capacitor. 
     
     
         25 . The device as claimed in  claim 24 , further comprising a first transistor connected between the first capacitor and the first end bit line and a second transistor connected between the second capacitor and the second end bit line, the first transistor being turned ON at least when one of the first memory cells is selected, and the second transistor being turned ON at least when one of the second memory cells is selected. 
     
     
         26 . A semiconductor device comprising:
 a sense amplifier including first and second nodes and configured to amplify, when activated, a potential difference between the first and second nodes;   a first bit line configured to be operatively coupled to the first node of the sense amplifier;   a plurality of word lines each intersecting the first bit line;   a plurality of memory cells each disposed at an associated one of intersections of the first bit line and the word lines;   a second bit line configured to be operatively coupled to the second node of the sense amplifier, the second bit line being shorter than the first bit line; and   a first capacitor configured to be connected to the second bit line at least when one of the word lines is activated, the second bit line being increased in capacitance by the first capacitor at least when one of the word lines is activated.   
     
     
         27 . The device as claimed in  claim 26 , further comprising a second capacitor that is configured to be connected to the second bit line at least when one of the word lines is activated, the second bit line being increased in capacitance by the first and second capacitors at least when one of the word lines is activated. 
     
     
         28 . The device as claimed in  claim 26 , wherein each of the memory cells comprises a cell transistor and a cell capacitor connected in series. 
     
     
         29 . A semiconductor device comprising:
 first and second sense amplifier each including first and second nodes and configured to amplify, when activated, a potential difference between the first and second nodes;   a first bit line configured to be operatively coupled to the first node of the first sense amplifier;   a plurality of first word lines each intersecting the first bit line;   a plurality of first memory cells each disposed at an associated one of intersections of the first bit line and the first word lines;   a second bit line configured to be operatively coupled to the first node of the second sense amplifier;   a plurality of second word lines each intersecting the second bit line;   a plurality of second memory cells each disposed at an associated one of intersections of the second bit line and the second word lines;   a third bit line configured to be operatively coupled to the second node of the first sense amplifier, the third bit line being shorter than the first bit line;   a fourth bit line configured to be operatively coupled to the second node of the second sense amplifier, the fourth bit line being shorter than the second bit line;   a first capacitor configured to be connected to the third bit line at least when one of the first word lines is activated, the third bit line being increased in capacitance by the first capacitor at least when one of the first word lines is activated; and   a second capacitor configured to be connected to the fourth bit line at least when one of the second word lines is activated, the fourth bit line being increased in capacitance by the second capacitor at least when one of the second word lines is activated.   
     
     
         30 . The device as claimed in  claim 29 , further comprising a third capacitor that is configured to be connected to the third bit line at least when one of the first word lines is activated, the third bit line being increased in capacitance by the first and third capacitors at least when one of the first word lines is activated. 
     
     
         31 . The device as claimed in  claim 30 , further comprising a fourth capacitor that is configured to be connected to the fourth bit line at least when one of the second word lines is activated, the fourth bit line being increased in capacitance by the second and fourth capacitors at least when one of the second word lines is activated. 
     
     
         32 . The device as claimed in  claim 29 , wherein each of the first and second memory cells comprises a cell transistor and a cell capacitor connected in series.