Semiconductor memory device and method of manufacturing the same

Abstract

A semiconductor memory device comprising a bit line extending in a first direction, a vertical gate cell including a gate oxide layer and a gate metal layer that are formed in a pillar shape, a lower electrode and a data storage material layer formed on the vertical gate cell, and an interconnection layer formed on the data storage material layer.

What is claimed is: 
     
         1 . A method of manufacturing a semiconductor memory device, comprising:
 forming a gate cell material layer on a bit line;   etching a portion of the gate cell material layer in a line shape in a direction that the bit line extends to form a line shape etched region;   forming a first spacer insulating layer in the line shape etched region;   performing an etch-back process on the first spacer insulating layer to expose the bit line and form an etch-back region;   forming a first oxide layer below the first spacer insulating layer;   forming a first buried insulating layer in the etch-back region;   etching the gate cell material layer in a direction perpendicular to the direction that the bit line extends to form a first trench;   forming a second spacer insulating layer in the first trench on sidewalls of the gate cell material layer;   performing an etch-back process on the second spacer insulating layer to expose the bit line;   forming a second oxide layer below the second spacer insulating layer;   forming a second buried insulating layer in the first trench;   removing the first spacer insulating layer and the second spacer insulating layer;   sequentially forming a gate oxide layer and a gate metal layer in a space formed by removing the first and second spacer insulating layer;   removing a portion of the gate oxide layer and the gate metal layer;   forming a third buried insulating layer in a space formed by removing the portion of the gate oxide layer and the gate metal layer;   removing an upper portion of the gate cell material layer;   sequentially forming a lower electrode and a data storage material layer in a space formed by removing the upper portion of the gate cell material layer; and   forming an interconnection layer on the data storage material layer.   
     
     
         2 . The method of  claim 1 , wherein the gate cell material layer includes a semiconductor material selected from the group consisting of silicon (Si), silicon germanium (Site), germanium (Ge), and gallium arsenide (GaAs). 
     
     
         3 . The method of  claim 2 , wherein the gate cell material layer includes a semiconductor material selected from the group consisting of an N-doped semiconductor material, a P-doped semiconductor material, and an undoped semiconductor material to form a source, a drain, and a channel in a direction perpendicular to the direction that the bit line extends. 
     
     
         4 . The method of  claim 1 , further comprising forming a silicide layer using a material selected from titanium (Ti), cobalt (Co), nickel (Ni), tungsten (W), platinum (Pt), lead (Pb), molybdenum (Mo) and tantalum (Ta) at an interface between the lower electrode and the gate cell material layer to reduce a contact resistance between the lower electrode and the gate cell material layer. 
     
     
         5 . The method of  claim 1 , wherein the data storage layer includes a resistive layer for constituting any one selected from the group consisting of a phase-change random access memory (PCRAM), a magnetic random access memory (MRAM), a spin-transfer torque MRAM (STTMRAM), and a polymer random access memory (PoRAM). 
     
     
         6 . The method of  claim 5 , wherein, when the data storage material layer includes a material for the PCRAM, the data storage material layer includes a material layer selected from tellurium (Te), selenium (Se), germanium (Ge), a compound thereof, and an alloy thereof. 
     
     
         7 . The method of  claim 6 , wherein the data storage material layer includes a material selected from the group consisting of Te, Se, Ge, bismuth (Bi), Pb, tin (Sn), arsenic (As), sulfur (S), Si, phosphorus (P), oxygen (O), nitrogen (N), a compound thereof, and an alloy thereof. 
     
     
         8 . The method of  claim 1 , wherein each of the bit line, the gate metal layer, the lower electrode, and the interconnection layer includes at least one of a metal, an alloy, a metal oxinitride, and a conductive carbon compound including tungsten (W), copper (Cu), titanium nitride (TIN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), niobium nitride (NbN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), titanium boron nitride (TiBN), zirconium silicon nitride (ZrSiN), tungsten silicon nitride (WSiN), tungsten boron nitride (WBN), zirconium aluminum nitride (ZrAlN), molybdenum silicon nitride (MoAlN), molybdenum aluminum nitride (MoAlN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), titanium (Ti), molybdenum (Mo), tantalum (Ta), titanium silicide (TiSi), tantalum silicide (TaSi), titanium tungsten (TiW), titanium oxynitride (TiON), titanium aluminum oxynitride (TIAION), tungsten oxynitride (WON), and tantalum oxynitride (TaON). 
     
     
         9 . The method of  claim 1 , wherein the interconnection layer is formed in a plate shape. 
     
     
         10 . The method of  claim 1 , further comprising forming a multi-stack structure including at least one cell having the same structure as a cell formed below the interconnection layer. 
     
     
         11 . A method of manufacturing a semiconductor memory device, comprising:
 forming a gate cell material layer on a bit line;   etching a portion of the gate cell material layer in a direction perpendicular to a direction that the bit line extends to form a first trench;   forming a spacer insulating layer in the first trench on sidewalls of the gate cell material layer;   forming an oxide layer below the space insulating layer;   forming a first buried insulating layer in the first trench;   removing the spacer insulating layer;   sequentially forming a gate oxide layer and a gate metal layer in a space formed by removing the spacer insulating layer;   removing a portion of the gate oxide layer and the gate metal layer;   forming a second buried insulating layer in a space formed by removing the portion of the gate oxide layer and the gate metal layer;   removing an upper portion of the gate cell material layer;   sequentially forming a lower electrode and a data storage material layer a space formed by removing the upper portion of the gate cell material layer; and   forming an interconnection layer on the data storage material layer.   
     
     
         12 . The method of  claim 11 , wherein the gate cell material layer includes a semiconductor material selected from the group consisting of silicon (Si), silicon germanium (SiGe), germanium (Ge), and gallium arsenide (GaAs). 
     
     
         13 . The method of  claim 12 , wherein the gate cell material layer includes a semiconductor material selected from the group consisting of an N-doped semiconductor material, a P-doped semiconductor material, and an undoped semiconductor material to form a source, a drain, and a channel in a direction perpendicular to the direction that the bit line extends. 
     
     
         14 . The method of  claim 11 , further comprising forming a silicide layer using a material selected from titanium (Ti), cobalt (Co), nickel (Ni), tungsten (W), platinum (Pt), lead (Pb), molybdenum (Mo) and tantalum (Ta) at an interface between the lower electrode and the gate cell material layer to reduce a contact resistance between the lower electrode and the gate cell material layer. 
     
     
         15 . The method of  claim 11 , wherein the data storage layer includes a resistive layer for constituting any one selected from the group consisting of a phase-change random access memory (PCRAM), a magnetic random access memory (MRAM), a spin-transfer torque MRAM (STTMRAM), and a polymer random access memory (PoRAM). 
     
     
         16 . The method of  claim 15 , wherein, when the data storage material layer includes a material for the PCRAM, the data storage material layer includes a material layer selected from tellurium (Te), selenium (Se), germanium (Ge), a compound thereof, and an alloy thereof. 
     
     
         17 . The method of  claim 16 , wherein the data storage material layer includes a material selected from the group consisting of Te, Se, Ge, bismuth (Bi), Pb, tin (Sn), arsenic (As), sulfur ( 5 ), Si, phosphorus (P), oxygen (O), nitrogen (N), a compound thereof, and an alloy thereof. 
     
     
         18 . The method of  claim 11 , wherein each of the bit line, the gate metal layer, the lower electrode, and the interconnection layer includes at least one of a metal, an alloy, a metal oxinitride, and a conductive carbon compound including tungsten (W), copper (Cu), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), niobium nitride (NbN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), titanium boron nitride (TiBN), zirconium silicon nitride (ZrSiN), tungsten silicon nitride (WSiN), tungsten boron nitride (WBN), zirconium aluminum nitride (ZrAlN), molybdenum silicon nitride (MoSiN), molybdenum aluminum nitride (MoAlN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), titanium (Ti), molybdenum (Mo), tantalum (Ta), titanium silicide (TiSi), tantalum silicide (TaSi), titanium tungsten (TiW), titanium oxynitride (TiON), titanium aluminum oxynitride (TiAlON), tungsten oxynitride (WON), and tantalum oxynitride (TaON). 
     
     
         19 . The method of  claim 11 , wherein the interconnection layer is formed in a plate shape. 
     
     
         20 . The method of  claim 11 , further comprising forming a multi-stack structure including at least one cell having the same structure as a cell formed below the interconnection layer. 
     
     
         21 . A method of manufacturing a semiconductor memory device, comprising:
 forming a gate cell material layer on a bit line;   patterning the gate cell material layer in a pillar shape;   forming an insulating layer in a bottom portion of a region where the gate cell material layer is removed;   forming a gate oxide layer on an exposed sidewall of the gate cell material layer;   forming a gate metal layer on the gate oxide layer in the region where the gate cell material layer is removed;   forming a first buried insulating layer in the region where the gate cell material layer is removed;   removing a portion of the gate oxide layer and the gate metal layer;   forming a second buried insulating layer in a space formed by removing the gate oxide layer and the gate metal layer;   removing an upper portion of the gate cell material layer;   sequentially forming a lower electrode and a data storage material layer in a space formed by removing the upper portion of the gate cell material layer; and   forming an interconnection layer on the data storage material layer.   
     
     
         22 . The method of  claim 21 , wherein the gate cell material layer includes a semiconductor material selected from the group consisting of silicon (Si), silicon germanium (SiGe), germanium (Ge), and gallium arsenide (GaAs). 
     
     
         23 . The method of  claim 21 , wherein the gate cell material layer includes a semiconductor material selected from the group consisting of an N-doped semiconductor material, a P-doped semiconductor material, and an undoped semiconductor material to form a source, a drain, and a channel in a direction perpendicular to the direction that the bit line extends. 
     
     
         24 . The method of  claim 21 , further comprising forming a silicide layer using a material selected from titanium (Ti), cobalt (Co), nickel (Ni), tungsten (W), platinum (Pt), lead (Pb), molybdenum (Mo) and tantalum (Ta) at an interface between the lower electrode and the gate cell material layer to reduce a contact resistance between the lower electrode and the gate cell material layer. 
     
     
         25 . The method of  claim 21 , wherein the data storage layer includes a resistive layer for constituting any one selected from the group consisting of a phase-change random access memory (PCRAM), a magnetic random access memory (MRAM), a spin-transfer torque MRAM (STTMRAM), and a polymer random access memory (PoRAM). 
     
     
         26 . The method of  claim 25 , wherein, when the data storage material layer includes a material for the PCRAM, the data storage material layer includes a material layer selected from tellurium (Te), selenium (Se), germanium (Ge), a compound thereof, and an alloy thereof. 
     
     
         27 . The method of  claim 26 , wherein the data storage material layer includes a material selected from the group consisting of Te, Se, Ge, bismuth (Bi), Pb, tin (Sn), arsenic (As), sulfur (S), Si, phosphorus (P), oxygen (O), nitrogen (N), a compound thereof, and an alloy thereof. 
     
     
         28 . The method of  claim 21 , wherein each of the bit line, the gate metal layer, the lower electrode, and the interconnection layer includes at least one of a metal, an alloy, a metal oxinitride, and a conductive carbon compound including tungsten (W), copper (Cu), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), niobium nitride (NbN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), titanium boron nitride (TiBN), zirconium silicon nitride (ZrSiN), tungsten silicon nitride (WSiN), tungsten boron nitride (WBN), zirconium aluminum nitride (ZrAlN), molybdenum silicon nitride (MoSiN), molybdenum aluminum nitride (MoAlN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), titanium (Ti), molybdenum (Mo), tantalum (Ta), titanium silicide (TiSi), tantalum silicide (TaSi), titanium tungsten (TiW), titanium oxynitride (TiON), titanium aluminum oxynitride (TiAlON), tungsten oxynitride (WON), and tantalum oxynitride (TaON). 
     
     
         29 . The method of  claim 21 , wherein the interconnection layer is formed in a plate shape. 
     
     
         30 . The method of  claim 31 , further comprising forming a multi-stack structure including at least one cell having the same structure as a cell formed below the interconnection layer. 
     
     
         31 . A semiconductor memory device, comprising:
 a bit line extending in a first direction;   a vertical gate cell including a gate oxide layer and a gate metal layer that are formed in a pillar shape;   a lower electrode and a data storage material layer formed on the vertical gate cell; and   an interconnection layer formed on the data storage material layer.   
     
     
         32 . The semiconductor memory device of  claim 31 , wherein the interconnection layer is formed in a plate shape. 
     
     
         33 . The method of  claim 31 , further comprising at least one cell having the same structure as a cell formed below the interconnection layer formed above the interconnection layer in a stack. 
     
     
         34 . A semiconductor memory device, comprising:
 a bit line;   a cell structure having a pattern shape formed on the bit line; and   a vertical gate structure formed on a sidewall of the cell structure.   
     
     
         35 . The semiconductor memory device of  claim 34 , further comprising a data storage material layer formed on the cell structure. 
     
     
         36 . A semiconductor memory device, comprising:
 a first bit line;   a first cell structure formed on the first bit line, wherein a gate electrode structure of the first cell structure is formed on an outer circumference of the first cell structure;   a first data storage material layer formed on the first cell structure;   a common source line formed on the first data storage material layer;   a second cell structure formed on the common source line, wherein a gate electrode structure of the second cell structure is formed on an outer circumference of the second cell structure;   a second data storage material layer formed on the second cell structure; and   a second bit line formed on the second data storage material layer.