Enhancement mode iii-nitride device and method for manufacturing thereof

Abstract

Enhancement mode III-nitride HEMT and method for manufacturing an enhancement mode III-nitride HEMT are disclosed. In one aspect, the method includes providing a substrate having a stack of layers on the substrate, each layer including a III-nitride material, and a passivation layer having high temperature silicon nitride overlying and in contact with an upper layer of the stack of III-nitride layers, wherein the HT silicon nitride is formed by MOCVD or LPCVD or any equivalent technique at a temperature higher than about 450° C. The method also includes forming a recessed gate region by removing the passivation layer only in the gate region, thereby exposing the underlying upper layer. The method also includes forming a p-doped GaN layer at least in the recessed gate region, thereby filling at least partially the recessed gate region, and forming a gate contact and source/drain contacts.

What is claimed is: 
     
         1 . A method of manufacturing an enhancement mode III-nitride high electron mobility transistor (HEMT), the method comprising:
 providing a substrate comprising a stack of layers on the substrate, each layer comprising a III-nitride material, and a passivation layer comprising high temperature (HT) silicon nitride overlying and in contact with an upper layer of the stack of III-nitride layers, wherein the HT silicon nitride is formed by metal-organic chemical vapor deposition (MOCVD) or low pressure chemical vapor deposition (LPCVD) at a temperature higher than about 450° C.;   forming a recessed gate region by removing substantially completely the passivation layer only in the gate region, thereby exposing the underlying upper layer;   forming a p-doped GaN layer at least in the recessed gate region, thereby filling at least partially the recessed gate region; and   forming a gate contact in the gate region and source/drain contacts through the passivation layer.   
     
     
         2 . The method according to  claim 1 , wherein the passivation layer is formed in-situ with the stack of III-nitride layers. 
     
     
         3 . The method according to  claim 1 , wherein the p-doped GaN layer is formed by selective epitaxial growth only in the recessed gate region. 
     
     
         4 . The method according to  claim 1 , wherein the p-doped GaN layer is formed by non-selective deposition both in the recessed gate region and on the passivation layer and wherein it is removed selectively from the passivation layer in a subsequent step. 
     
     
         5 . The method according to  claim 4 , wherein the p-doped GaN layer formed on the passivation layer is a polycrystalline material. 
     
     
         6 . The method according to  claim 1 , wherein the thickness of the passivation layer is between about 5 nm and 300 nm. 
     
     
         7 . The method according to  claim 1 , wherein the thickness of the p-GaN layer in the recessed gate region is between about 5 nm and 300 nm. 
     
     
         8 . The method according to  claim 1 , wherein the doping concentration of the p-GaN layer is higher than about 1×10 17  cm −3 . 
     
     
         9 . The method according to  claim 1 , wherein the p-dopants comprise Mg, Be, Zn or combinations thereof. 
     
     
         10 . The method according to  claim 1 , wherein the HT silicon nitride is formed at a temperature higher than about 550° C. 
     
     
         11 . The method according to  claim 10 , wherein the HT silicon nitride is formed at a temperature higher than about 700° C. 
     
     
         12 . An enhancement mode III-nitride high electron mobility transistor (HEMT) as manufactured by the method according to  claim 1 . 
     
     
         13 . An enhancement mode III-nitride high electron mobility transistor (HEMT) comprising:
 a substrate comprising a stack of layers on the substrate, each layer comprising a III-nitride material, and a passivation layer comprising high temperature (HT) silicon nitride overlying and in contact with an upper layer of the stack of III-nitride layers;   a recessed gate region through the passivation layer exposing at its bottom the upper layer of the stack of III-nitride layers;   a p-doped GaN layer filling at least partially the recessed gate region, wherein the p-doped GaN layer is overlying and in contact with the upper layer of the stack of III-nitride layers in the recessed gate region; and   source/drain contacts provided through the passivation layer,   wherein the passivation layer covers the upper layer of the stack of III-nitride layers everywhere except the recessed gate region and the source/drain contacts.   
     
     
         14 . The device according to  claim 13 , wherein the passivation layer comprises high temperature (HT) silicon nitride, formed by metal-organic chemical vapor deposition (MOCVD) or low pressure chemical vapor deposition (LPCVD) having a H-content of about 3-8% and a density of about 2.9-3.1 g/cm 3 . 
     
     
         15 . The device according to  claim 13 , wherein the thickness of the passivation layer is between about 5 nm and 300 nm. 
     
     
         16 . The device according to  claim 13 , wherein the thickness of the p-GaN layer in the recessed gate region is between about 5 nm and 300 nm. 
     
     
         17 . The device according to  claim 13 , wherein the doping concentration of the p-GaN layer is higher than about 1×10 17  cm −3 . 
     
     
         18 . The device according to  claim 13 , wherein the p-dopants comprise Mg, Be, Zn or any combinations thereof. 
     
     
         19 . The device according to  claim 13 , wherein the p-doped GaN layer is formed only in the recessed gate region.