Three-dimensional non-volatile memory device, memory system and method of manufacturing the same

Abstract

A three-dimensional (3-D) non-volatile memory device includes channel structures each including channel layers stacked over a substrate and extending in a first direction, wherein the channel layers include well regions, respectively, vertical gates located and spaced from each other between the channel structures, and a well pick-up line contacting on the well regions of the channel layers and extending in a second direction crossing the channel structures.

What is claimed is: 
     
         1 . A three-dimensional (3-D) non-volatile memory device, comprising:
 channel structures each including channel layers stacked over a substrate and extending in a first direction, wherein the channel layers include well regions, respectively;   vertical gates located and spaced from each other between the channel structures; and   a well pickup line contacting on the well regions of the channel layers and extending in a second direction crossing the channel structures.   
     
     
         2 . The 3-D non-volatile memory device of  claim 1 , further comprising:
 word lines coupled to the vertical gates and extending in the second direction crossing the channel structures; and   a memory layer interposed between the channel structures and the vertical gates, and between the channel structures and each of the word lines.   
     
     
         3 . The 3-D non-volatile memory device of  claim 1 , further comprising junctions formed in the channel layers exposed between the vertical gates. 
     
     
         4 . The 3-D non-volatile memory device of  claim 3 , wherein the channel layers include P type impurities at a low concentration, the junctions include N type impurities and the well regions include the P type impurities at a high concentration. 
     
     
         5 . The 3-D non-volatile memory device of  claim 1 , further comprising:
 source regions formed in each of the channel layers; and   a source line contacting on the source regions of the channel layers and extending in the second direction crossing the channel structures.   
     
     
         6 . The 3-D non-volatile memory device of  claim 5 , wherein the channel layers include P type impurities at a low concentration, the source regions include N type impurities and the well regions include the P type impurities at a high concentration. 
     
     
         7 . A memory system, comprising:
 a three-dimensional (3-D) non-volatile memory device including channel structures each having channel layers that are stacked over a substrate and includes respective well regions, vertical gates located and spaced from each other between the channel structures, and a well pickup line contacting on the well regions of the channel layers and extending in a direction crossing the channel structures; and   a memory controller configured to control the 3-D non-volatile memory device.   
     
     
         8 . The memory system of  claim 7 , further comprising junctions formed in the channel layers exposed between the vertical gates. 
     
     
         9 . The memory system of  claim 7 , further comprising:
 source regions formed in each of the channel layers; and   a source line contacting on the source regions of the channel layers and extending in the direction crossing the channel structures.   
     
     
         10 . A method of manufacturing a three-dimensional (3-D) non-volatile memory device, the method comprising:
 forming channel structures each including channel layers and interlayer insulating layers stacked alternately over a substrate, wherein the channel layers include well regions, respectively;   forming vertical gates spaced from each other between the channel structures; and   forming a well pickup line contacting on the well regions of the channel layers and extending in a direction crossing the channel structures.   
     
     
         11 . The method of  claim 10 , wherein the forming of the channel structures comprises:
 alternately forming the interlayer insulating layers and the channel layers over the substrate; and   etching the interlayer insulating layers and the channel layers to form the channel structures extending in parallel along one direction.   
     
     
         12 . The method of  claim 11 , wherein the forming of the interlayer insulating layers and the channel layers comprises:
 doping a portion of each of the channel layers with impurities to form a well region after forming the each of the channel layers.   
     
     
         13 . The method of  claim 11 , wherein the forming of the channel structures further comprises:
 forming a mask pattern exposing portions of the channel structures corresponding to the well regions of the channel layers; and   forming the well regions in the channel layers by doping the channel layers with impurities by using the mask pattern as a barrier.   
     
     
         14 . The method of  claim 10 , wherein the forming of the vertical gates comprises:
 forming a memory layer over an entire surface of the channel structures;   forming a conductive layer on the memory layer; and   forming the vertical gates and word lines coupled to the vertical gates by etching the conductive layer and the memory layer, wherein the word lines extend in the direction crossing the channel structures.   
     
     
         15 . The method of  claim 10 , further comprising:
 forming a mask pattern covering the well regions of the channel layers after the forming of the vertical gates; and   forming junctions in each of the channel layers between the vertical gates and source regions in portions of the channel layers by doping the channel layers exposed between the mask pattern and the vertical gates with impurities.   
     
     
         16 . The method of  claim 15 , wherein the forming of the junctions and the source regions is performed by using a tilting ion implantation process or a plasma doping process. 
     
     
         17 . The method of  claim 15 , further comprising forming a source line coupled to the source regions of the channel layers and extending in the direction crossing the channel structures.