Semiconductor stack packages and methods of fabricating the same

Abstract

Semiconductor chip stacks are provided. The semiconductor chip stack includes a semiconductor chip stack including a plurality of first semiconductor chips vertically stacked on a top surface of the interposer, a second semiconductor chip stacked on a bottom surface of the interposer opposite to the semiconductor chip stack, and an external electrode attached to a top surface of the second semiconductor chip opposite to the interposer. Electronic systems including the semiconductor chip stack and related methods are also provided.

What is claimed is: 
     
         1 . A semiconductor stack package, comprising:
 an interposer;   a semiconductor chip stack including a plurality of first semiconductor chips vertically stacked on a top surface of the interposer;   a second semiconductor chip stacked on a bottom surface of the interposer opposite to the semiconductor chip stack; and   an external electrode attached to a top surface of the second semiconductor chip opposite to the interposer.   
     
     
         2 . The semiconductor stack package of  claim 1 , further comprising:
 a first through electrode penetrating the interposer;   a second through electrode that penetrates the first semiconductor chips to electrically connect the first semiconductor chips to the first through electrode; and   a third through electrode that penetrates the second semiconductor chip to electrically connect the first through electrode to the external electrode.   
     
     
         3 . A semiconductor stack package, comprising:
 an interposer in which a first through electrode is inserted;   a semiconductor chip stack including a plurality of first semiconductor chips vertically stacked on a top surface of the interposer;   a second through electrode that penetrates the semiconductor chip stack to be electrically connected to the first through electrode;   a second semiconductor chip on a bottom surface of the interposer; and   a third through electrode that penetrates the second semiconductor chip to be electrically connected to the first through electrode.   
     
     
         4 . The semiconductor stack package of  claim 3 , further comprising a protection layer covering the semiconductor chip stack. 
     
     
         5 . The semiconductor stack package of  claim 3 , wherein each of the plurality of first semiconductor chips includes a memory chip. 
     
     
         6 . The semiconductor stack package of  claim 3 , wherein the second semiconductor chip includes a logic chip. 
     
     
         7 . The semiconductor stack package of  claim 3 , further comprising a protection layer covering the second semiconductor chip. 
     
     
         8 . The semiconductor stack package of  claim 7 , wherein the protection layer covers sidewalls of the second semiconductor chip and to expose a top surface of the second semiconductor chip opposite to the interposer. 
     
     
         9 . The semiconductor stack package of  claim 3 , further comprising an external electrode electrically connected to the third through electrode. 
     
     
         10 . A method of fabricating a semiconductor stack package, the method comprising:
 vertically stacking a plurality of first semiconductor chips on a top surface of an interposer to form a semiconductor chip stack; and   stacking a second semiconductor chip on a bottom surface of the interposer opposite to the semiconductor chip stack.   
     
     
         11 . The method of  claim 10 , further comprising:
 forming a first through electrode that penetrates a body of the interposer,   wherein one end of the first through electrode is exposed at the top surface of the interposer to constitute a first contact portion, and an other end of the first through electrode is exposed at the bottom surface of the interposer to constitute a second contact portion.   
     
     
         12 . The method of  claim 11 , wherein the semiconductor chip stack is formed to include a second through electrode that penetrates the plurality of first semiconductor chips to electrically connect the first semiconductor chips to each other, and the second through electrode is electrically connected to the first through electrode. 
     
     
         13 . The method of  claim 11 , wherein the second semiconductor chip is formed to include a second through electrode that penetrates a body of the second semiconductor chip, and the second through electrode is electrically connected to the first through electrode. 
     
     
         14 . The method of  claim 13 , further comprising attaching an external electrode to the second through electrode. 
     
     
         15 . The method of  claim 10 , wherein the interposer is a substrate including silicon material.