Policies for Shader Resource Allocation in a Shader Core

Abstract

A method of determining priority within an accelerated processing device is provided. The accelerated processing device includes compute pipeline queues that are processed in accordance with predetermined criteria. The queues are selected based on priority characteristics and the selected queue is processed until a time quantum lapses or a queue having a higher priority becomes available for processing.

What is claimed is: 
     
         1 . A method of determining priority within an accelerated processing device (APD) including compute pipelines, comprising:
 selecting a first queue and a second queue from the compute pipeline processing queues within each of the compute pipelines in accordance with predetermined criteria; and   selecting one of the first and second queues for processing in accordance with priority criteria;   wherein the selected queue is processed until at least one from the group including (i) lapse of a time quantum and (ii) a queue having a higher priority becomes available.   
     
     
         2 . The method of  claim 1 , wherein processing the selected queue comprises preempting the selected queue. 
     
     
         3 . The method of  claim 2 , wherein preempting the selected queue comprises performing a context switching operation on the selected queue. 
     
     
         4 . The method of  claim 2 , further comprising initiating processing of a second queue after the preempting. 
     
     
         5 . The method of  claim 1 , further comprising determining a relative priority of each of the compute pipelines. 
     
     
         6 . The method of  claim 5 , wherein the relative priority of each of the compute pipelines is determined using a least recently issued circuit. 
     
     
         7 . The method of  claim 6 , wherein the least recently issued circuit is a totem pole circuit. 
     
     
         8 . The method of  claim 6 , further comprising assigning the compute pipeline having the lowest priority to the bottom the circuit. 
     
     
         9 . The method of  claim 1 , wherein the first queue is a ready queue. 
     
     
         10 . The method of  claim 1 , wherein the second queue is an active queue. 
     
     
         11 . The method of  claim 1 , wherein the predetermined criteria include (i) a queue priority, (ii) a queue quantum duration, and (iii) a queue ready control. 
     
     
         12 . A system, comprising:
 a memory; and   an accelerated processing device (APD) including compute pipelines coupled to the memory, wherein the compute pipelines are configured to, based on an instruction stored in memory,   select a first queue and a second queue from compute pipeline processing queues within each of the compute pipelines in accordance with predetermined criteria;   select one of the first and second queues for processing in accordance with priority criteria; and   process the selected queue until at least one from the group including (i) lapse of a time quanta and (ii) a queue having a higher priority becomes available.   
     
     
         13 . The system of  claim 12 , wherein the compute pipelines are configured to preempt processing the selected queue. 
     
     
         14 . The system of  claim 13 , wherein the compute pipelines are configured to context the selected queue during the preempting. 
     
     
         15 . The system of  claim 13 , wherein the compute pipelines are configured to initiate processing of a second queue after the preempting. 
     
     
         16 . The system of  claim 12 , further comprising a shader input block coupled to the compute pipelines and configured to determine a relative priority of each of the compute pipelines. 
     
     
         17 . The system of  claim 16 , wherein the relative priority of each of the compute pipelines is determined using a least recently issued circuit. 
     
     
         18 . The system of  claim 17 , wherein the least recently issued circuit is a totem pole circuit. 
     
     
         19 . The system of  claim 17 , further comprising assigning the compute pipeline having the lowest priority to the bottom of the circuit. 
     
     
         20 . The method of  claim 12 , wherein the first queue is a ready queue. 
     
     
         21 . The method of  claim 12 , wherein the second queue is an active queue. 
     
     
         22 . The method of  claim 12 , wherein the predetermined criteria include (i) a queue priority, (ii) a queue quantum duration, and (iii) a queue ready control.