Semiconductor apparatus and repairing method thereof

Abstract

A semiconductor apparatus includes a semiconductor chip through-line for transmitting signals commonly to a plurality of stacked semiconductor chips. The apparatus includes a first test pulse signal transmission unit configured to transmit a first test pulse signal to a first end of the semiconductor chip through-line when a power-up operation is performed; a second test pulse signal transmission unit configured to transmit a second test pulse signal to a second end of the semiconductor chip through-line after the first test pulse signal is transmitted; a first signal reception unit coupled to the first end of the semiconductor chip through-line, and configured to receive signals transmitted from the first and second test pulse signal transmission units; and a second signal reception unit coupled to the second end of the semiconductor chip through-line, and configured to receive the signals transmitted by the first and second test pulse signal transmission units.

What is claimed is: 
     
         1 . A method for repairing a semiconductor apparatus for transmitting signals commonly to a plurality of stacked semiconductor chips, the method comprising the steps of:
 transmitting a first test pulse signal to first ends of semiconductor chip through-lines in response to a power-up signal;   receiving the first test pulse signal through first and second signal reception units, which are coupled to first and second ends of the semiconductor chip through-lines;   transmitting a second test pulse signal to the second ends of the semiconductor chip through-lines;   receiving the second test pulse signal through the first and second signal reception units, which are coupled to the first and second ends of the semiconductor chip through-lines; and   repairing the semiconductor chip through-lines based on the first and second test pulse signals received by the first and second signal reception units.   
     
     
         2 . The method according to  claim 1 , wherein the second test pulse signal is transmitted to the second ends of the semiconductor chip through-lines after the first test pulse signal is transmitted to the first ends of the semiconductor chip through-lines. 
     
     
         3 . The method according to  claim 1 , wherein the second test pulse signal is transmitted to the second ends of the semiconductor chip through-lines when the first test pulse signal transmitted through the first ends of the semiconductor chip through-lines is received at a predetermined level.