Semiconductor devices having polysilicon gate patterns and methods of fabricating the same

Abstract

A semiconductor device including a gate insulation pattern on a substrate, and a semiconductor gate pattern including an amorphous silicon pattern and a polycrystalline silicon pattern stacked on a side of the gate insulation pattern opposite to the substrate. The amorphous silicon pattern includes anti-diffusion impurities that suppress diffusion of impurity ions in the semiconductor gate pattern.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a semiconductor gate pattern including a polycrystalline silicon pattern formed over an amorphous silicon pattern, wherein the amorphous silicon pattern includes anti-diffusion impurities and is configured to suppress diffusion of impurity ions.   
     
     
         2 . The semiconductor device of  claim 1 , further comprising:
 a gate insulation pattern formed beneath the semiconductor gate pattern in a substrate, and wherein   the semiconductor gate pattern is stacked on an opposite side of the gate insulation pattern as the substrate, and a bottom surface of the amorphous silicon pattern directly contacts a top surface of the gate insulation pattern, and a top surface of the amorphous silicon pattern directly contacts a bottom surface of the polycrystalline silicon pattern.   
     
     
         3 . The semiconductor device of  claim 1 , wherein a thickness of the amorphous silicon pattern is equal to or less than one third a thickness of the semiconductor gate pattern. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the anti-diffusion impurities include nitrogen atoms, carbon atoms, or oxygen atoms. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the semiconductor gate pattern has a thickness that is less than or equal to about 1000 angstroms (Π), and the amorphous silicon pattern has a thickness that is less than or equal to about 200 angstroms (Π). 
     
     
         6 . The semiconductor device of  claim 1 , wherein a maximum impurity ion concentration of the amorphous silicon pattern is at least fifty times greater than an impurity ion concentration in a lower portion of the polycrystalline silicon pattern adjacent to the amorphous silicon pattern. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the polycrystalline silicon pattern is formed not including anti-diffusion impurities. 
     
     
         8 . A method of fabricating a semiconductor device, the method comprising:
 forming an amorphous silicon pattern;   forming a polycrystalline pattern over the amorphous silicon pattern to form a semiconductor gate pattern,   wherein the amorphous silicon pattern includes anti-diffusion impurities and is configured to suppress diffusion of impurity ions.   
     
     
         9 . The method of  claim 8 , further comprising forming a gate insulation pattern beneath the semiconductor gate pattern on a substrate wherein the semiconductor gate pattern is stacked on an opposite side of the gate insulation pattern as the substrate, and a bottom surface of the amorphous silicon pattern directly contacts a top surface of the gate insulation pattern, and a top surface of the amorphous silicon pattern directly contacts a bottom surface of the polycrystalline silicon pattern. 
     
     
         10 . The method of  claim 8 , further comprising:
 forming a gate insulation layer on a substrate;   forming a first amorphous silicon layer doped with anti-diffusion impurities on a side of the gate insulation layer opposite to the substrate;   forming a second amorphous silicon layer on a side of the first amorphous silicon layer opposite to the gate insulation layer; and   selectively crystallizing the second amorphous silicon layer to form a polycrystalline silicon layer,   wherein the first amorphous silicon layer is doped with the anti-diffusion impurities and the polycrystalline silicon layer constitutes a semiconductor gate layer, and   wherein the semiconductor gate layer and the gate insulation layer are patterned to form the gate insulation pattern, an amorphous silicon pattern and a polycrystalline silicon pattern sequentially stacked on the substrate after the impurity ions in the semiconductor gate layer are activated.   
     
     
         11 . The method of  claim 10 , further comprising:
 forming the polycrystalline silicon pattern using a first etching process and forming the amorphous silicon pattern using a second etching process, and   wherein the second etching process is performed using an etch recipe that exhibits less etch damage than the first etching process.   
     
     
         12 . The method of  claim 10 , wherein the anti-diffusion impurities suppress crystallization of the first amorphous silicon layer and the second amorphous silicon layer is selectively crystallized. 
     
     
         13 . The method of  claim 10 , wherein the anti-diffusion impurities are injected into the first amorphous silicon layer during formation of the first amorphous silicon layer. 
     
     
         14 . The method of  claim 10 , wherein the anti-diffusion impurities are injected into the first amorphous silicon layer after deposition of the first amorphous silicon layer. 
     
     
         15 . The method of  claim 10 , wherein the first amorphous silicon layer is formed to a thickness which is equal to or less than one third a thickness of the semiconductor gate layer. 
     
     
         16 . The method of  claim 10 , wherein the anti-diffusion impurities include nitrogen atoms, carbon atoms or oxygen atoms. 
     
     
         17 . The method of  claim 10 , wherein the second amorphous silicon layer is selectively crystallized using a rapid thermal annealing process performed at a temperature of about 800° C. to about 1000° C. 
     
     
         18 . The method of  claim 10 , further comprising injecting the impurity ions into the semiconductor gate layer after the second amorphous silicon layer is selectively crystallized, and annealing the semiconductor gate layer at a temperature of about 900° C. to about 1000° C. to activate the impurity ions in the semiconductor gate layer after the impurity ions are injected into the semiconductor gate layer. 
     
     
         19 . A semiconductor device comprising:
 a semiconductor gate pattern comprising a plurality of polycrystalline silicon patterns comprised of at least a first and second polycrystalline silicon pattern, and a plurality of amorphous silicon patterns comprised of at least a first and second amorphous silicon pattern, that are stacked to form a semiconductor gate pattern, wherein the plurality of amorphous silicon patterns each include anti-diffusion impurities and are configured to suppress diffusion of impurity ions   
     
     
         20 . The semiconductor device of  claim 19 , wherein the plurality of amorphous silicon patterns and the plurality of amorphous silicon patterns are alternately stacked on a gate insulation pattern over a substrate.