Information processing apparatus and unauthorized access prevention method

Abstract

An information processing apparatus includes nodes having a first node and a second node each of which includes a processor and a memory in which at least a part of area is set as a shared memory area, and an interconnect that connects the nodes. The first node transmits communication data to be transmitted to the second node by attaching identification information used for accessing a memory in the second node. The second node determines whether or not an access to the shared memory area in the memory in the second node is permitted on the basis of the identification information that is attached to the communication data transmitted from the first node and identification information stored in a storing unit and used for controlling permission to access, from another node, the shared memory area in the memory in the second node.

What is claimed is: 
     
         1 . An information processing apparatus comprising:
 a plurality of nodes having a first node and a second node each of which includes a processor and a memory in which at least a part of area is set as a shared memory area; and   an interconnect that connects the nodes, wherein   the first node includes a processor executing:
 transmitting communication data to be transmitted to the second node by attaching identification information stored in a first storing unit and used for accessing a memory in the second node, and 
   the second node includes a processor executing:
 determining whether or not an access to the shared memory area in the memory in the second node is permitted on the basis of the identification information that is attached to the communication data transmitted from the first node and identification information stored in a second storing unit and used for controlling permission to access, from another node, the shared memory area in the memory in the second node. 
   
     
     
         2 . The information processing apparatus according to  claim 1 , wherein
 the processor included in the first node further executes storing, in the first storing unit, the identification information notified by the second node,   the processor included in the second node further executes:
 notifying the first node of a new piece of identification information; and 
 changing the identification information stored in the second storing unit to the identification information notified at the notifying, and 
   the determining includes permitting, when the identification information attached to the communication data transmitted from the first node matches the identification information stored in the second storing unit, access to the shared memory area in the memory in the second node, and not permitting, when the identification information attached to the communication data transmitted from the first node does not match the identification information stored in the second storing unit, access to the shared memory area in the memory in the second node.   
     
     
         3 . The information processing apparatus according to  claim 2 , wherein
 the processor included in the first node includes a cache memory that retains data obtained from the memory in the second node,   the processor included in the second node further executes writing the data retained by the cache memory included in the processor in the first node back to the memory in the second node, when the access for retaining data from the memory in the second node to the cache memory in the first node is not permitted at the determining, and   the changing includes changing the identification information stored in the second storing unit to the new piece of identification information, before the data is written back to the memory in the second node at the writing.   
     
     
         4 . The information processing apparatus according to  claim 2 , wherein
 the notifying includes notifying the first node of the new piece of identification information together with an instruction to stop access, and   the changing includes changing the identification information stored in the second storing unit to the new piece of identification information notified at the notifying, after a predetermined time has elapsed from when notifying the first node of the instruction to stop the access.   
     
     
         5 . The information processing apparatus according to  claim 2 , wherein
 the notifying includes notifying the first node of the new piece of identification information,   the changing includes changing the identification information stored in the second storing unit to the new piece of identification information, and   the processor included in the first node further executes retransmitting, when the access to the shared memory area in the memory in the second node is not permitted at the determining, the communication data for requesting the same access.   
     
     
         6 . The information processing apparatus according to  claim 5 , wherein
 the processor included in the second node further executes writing the data retained by the cache memory included in the processor in the first node back to the memory in the second node, when the access to the shared memory area in the memory in the second node is not permitted at the determining.   
     
     
         7 . The information processing apparatus according to  claim 1 , wherein the processor included in the first node uses a part of a register used for stacking data when a context switch is performed, as the first storing unit. 
     
     
         8 . The information processing apparatus according to  claim 1 , wherein the processor included in the first node includes the first storing unit, the number of which is the same as the number of threads executed in parallel by the processor. 
     
     
         9 . An unauthorized access prevention method executed by an information processing apparatus that includes a plurality of nodes having a first node and a second node each of which includes a processor and a memory in which at least a part of area is set as a shared memory area, and an interconnect that connects the nodes, the unauthorized access prevention method comprising:
 transmitting, using a processor included in the first node, identification information used for accessing a memory in the second node and attached to communication data to be transmitted to the second node;   obtaining, using a processor included in the second node, identification information used for controlling permission to access, from another node, the shared memory area in a memory in the second node; and   determining, using the processor included in the second node, whether or not an access to the shared memory area in the memory in the second node is permitted on the basis of the identification information that is attached to the communication data transmitted from the first node and the identification information obtained at the obtaining.