Semiconductor device having vertical channel transistor and manufacturing method of the same

Abstract

A semiconductor device having a vertical channel transistor and a method for manufacturing the same are provided. In the semiconductor device, a metal bit line is formed between vertical channel transistors, and the metal bit line is connected to only one of the vertical channel transistors through an asymmetric bit line contact. Through such a structure, the resistance of the bit line can be improved and the process margin for formation of the bit line can be secured.

1 - 6 . (canceled) 
     
     
         7 . A method for manufacturing a semiconductor device, the method comprising:
 etching a silicon substrate to form a first pillar and a second pillar separated from each other by a predetermined interval;   forming junction regions under the first pillar and the second pillar;   forming a bit line contact at a sidewall of the junction region of the first pillar, and forming an insulating film at a sidewall of the junction region of the second pillar; and   forming a bit line contacting the bit line contact in a space between the bit line contact and the insulating film.   
     
     
         8 . The method according to  claim 7 , wherein the etching-a-silicon-substrate-to-form-a-first-pillar-and-a-second-pillar comprises forming a buffer oxide film at sidewalls of the first pillar and the second pillar and over the silicon substrate between the first pillar and the second pillar. 
     
     
         9 . The method according to  claim 7 , wherein the forming junction-regions-under-the-first-pillar-and-the-second-pillar comprises:
 forming an impurity region by implanting first impurities into the silicon substrate between the first pillar and the second pillar;   etching the impurity region to a predetermined depth to form a first trench, and forming a spacer nitride film inside the first trench and over the first pillar and the second pillar; and   etching a lower portion of the first trench to form a second trench separating the impurity region formed under the first pillar and the impurity region formed under the second pillar.   
     
     
         10 . The method according to  claim 9 , further comprising oxidizing the silicon substrate exposed by the second trench to form a separation oxide film. 
     
     
         11 . The method according to  claim 9 , wherein the forming-a-bit-line-contact and forming-an-insulating-film comprise:
 implanting second impurities into only the spacer nitride film formed at the sidewall of the first pillar of the first and second pillars facing each other, with the bit line being interposed therebetween;   selectively removing the spacer nitride film into which the second impurities are implanted;   forming a first metal film at the sidewall of the first pillar, and performing a thermal treatment on the first metal film; and   selectively removing the first metal film so that only a portion of the first metal film silicided by the thermal treatment remains.   
     
     
         12 . The method according to  claim 11 , wherein the implanting-second-impurities-into-only-the-spacer-nitride-film is performed by a tilted ion implantation of the second impurities. 
     
     
         13 . The method according to  claim 11 , wherein the second impurities comprise boron ions (BF2). 
     
     
         14 . The method according to  claim 11 , wherein the first metal film comprises one of a cobalt (Co) film, a titanium (Ti) film, a tungsten (W) film, and a nickel (Ni) film. 
     
     
         15 . The method according to  claim 11 , wherein the forming-a-bit-line comprises:
 forming a second metal film in a space between the bit line contact and the insulating film so that the second metal film contacts the bit line contact; and   forming a third metal film to bury the second metal line.   
     
     
         16 . The method according to  claim 9 , wherein the forming-a-bit-line-contact and forming-an-insulating-film comprise:
 filling a space between the first pillar and the second pillar with polysilicon;   etching the polysilicon to expose only the spacer nitride film formed at the sidewall of the first pillar of the first and second pillars facing each other, with the bit line being interposed therebetween;   removing the exposed spacer nitride film; and   removing the polysilicon.   
     
     
         17 . The method according to  claim 16 , wherein the removing-the-exposed-spacer-nitride-film is performed by a cleaning process using phosphoric acid. 
     
     
         18 . The method according to  claim 7 , wherein the forming junction-regions-under-the-first-pillar-and-the-second-pillar comprises:
 forming an impurity region by implanting first impurities into the silicon substrate between the first pillar and the second pillar;   etching the impurity region to a predetermined depth to form a first trench, and forming a spacer nitride film inside the first trench and over the first pillar and the second pillar;   etching a lower portion of the first trench to form a second trench; and implanting impurities having a conductivity type opposite to the impurity region into a lower portion of the second trench.