Parallel processing processor system

Abstract

A parallel processing processor system includes multiple processor elements, a main memory, and a shared memory, whose latency with the processors is less than the latency between the main memory and the processors. Each of the multiple processor elements has a DSP (Digital Signal Processor) and an instruction cache. Firmware executed by the DSPs is transferred from the main memory to the shared memory and is shared by the DSPs. Updating of the instruction caches in the case where a cache miss has occurred is performed by, for example, copying, into the instruction caches, the content of the shared memory corresponding to an address accessed by a DSP.

1 . A parallel processing processor system that includes multiple processors and performs parallel processing on data read out from a main memory using the multiple processors, the system comprising:
 multiple processor elements, each processor element including a processor and a cache that holds an instruction corresponding to at least part of a program executed by the processor;   a shared memory, whose latency with the processors is less than the latency between the main memory and the processors, that stores the program transferred from the main memory and is shared by the multiple processor elements;   an update unit that updates the instruction in the cache with an instruction in the program stored in the shared memory in the case where a cache miss has occurred in the cache;   a transfer control unit that controls transfers between the main memory and the shared memory; and   a synchronization control unit that requests the transfer control unit to rewrite the program in the shared memory in response to a synchronizing signal.   
     
     
         2 . The parallel processing processor system according to  claim 1 , wherein the capacity of the cache is smaller than the capacity of the shared memory. 
     
     
         3 . The parallel processing processor system according to  claim 1 , wherein in the case where the cache miss has occurred in the cache, the update unit performs the update by copying, into the cache, the content of the shared memory corresponding to an address that the processor accessed. 
     
     
         4 . (canceled) 
     
     
         5 . The parallel processing processor system according to  claim 1 , wherein each of the multiple processors outputs the synchronizing signal upon completing the execution of the program currently stored in the shared memory, and the synchronization control unit requests the program in the shared memory to be rewritten in response to the synchronizing signal being outputted by all of the multiple processors. 
     
     
         6 . The parallel processing processor system according to  claim 1 , wherein each of the multiple processor elements further include a local memory that stores data to be processed read out from the main memory. 
     
     
         7 . The parallel processing processor system according to  claim 1 , wherein the shared memory operates in a higher frequency than the main memory. 
     
     
         8 . The parallel processing processor system according to  claim 1 , wherein the transfer control unit transfers the program from the main memory to the shared memory in Direct Memory Access (DMA). 
     
     
         9 . The parallel processing processor system according to  claim 1 , wherein at least one of the processors executes at least one of shading correction, MTF correction, color conversion processing, filter processing, and gamma processing on the data. 
     
     
         10 . The parallel processing processor system according to  claim 1 , wherein at least one of the processors executes at least one of binarization processing, halftone processing, color conversion processing, resolution conversion, smoothing, and darkness correction on the data. 
     
     
         11 . A method for a parallel processing processor system that includes multiple processors and performs parallel processing on data read out from a main memory using the multiple processors, wherein the system comprises multiple processor elements, each processor element including a processor and a cache that holds an instruction corresponding to at least part of a program executed by the processor, and a shared memory, whose latency with the processors is less than the latency between the main memory and the processors, that stores the program transferred from the main memory and is shared by the multiple processor elements,
 wherein the method comprises: 
 updating the instruction in the cache with an instruction in the program stored in the shared memory in the case where a cache miss has occurred in the cache; 
 controlling transfers between the main memory and the shared memory; and 
 requesting to rewrite the program in the shared memory in response to a synchronizing signal. 
 
     
     
         12 . A non-transitory computer-readable storage medium storing a program for causing a computer to execute a method for a parallel processing processor system that includes multiple processors and performs parallel processing on data read out from a main memory using the multiple processors, wherein the system comprises multiple processor elements, each processor element including a processor and a cache that holds an instruction corresponding to at least part of a program executed by the processor, and a shared memory, whose latency with the processors is less than the latency between the main memory and the processors, that stores the program transferred from the main memory and is shared by the multiple processor elements,
 wherein the method comprises:   updating the instruction in the cache with an instruction in the program stored in the shared memory in the case where a cache miss has occurred in the cache;   controlling transfers between the main memory and the shared memory; and   requesting to rewrite the program in the shared memory in response to a synchronizing signal.