US2013181265A1PendingUtilityA1

Methods of Forming a Gate Cap Layer Above a Replacement Gate Structure and a Semiconductor Device That Includes Such a Gate Structure and Cap Layer

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Assignee: GRASSHOFF GUNTERPriority: Jan 18, 2012Filed: Jan 18, 2012Published: Jul 18, 2013
Est. expiryJan 18, 2032(~5.5 yrs left)· nominal 20-yr term from priority
H10P 95/064H10P 52/403H10P 50/283H10W 20/077H10W 20/069H10D 64/017
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Claims

Abstract

Disclosed herein are various methods of forming a gate cap layer above a replacement gate structure, and a device having such a cap layer. In one example, a device disclosed herein includes a replacement gate structure having a dished upper surface, sidewall spacers positioned proximate the replacement gate structure and a gate cap layer positioned above the replacement gate structure, wherein the gate cap layer has a bottom surface that corresponds to the dished upper surface of the replacement gate structure.

Claims

exact text as granted — not AI-modified
What is claimed: 
     
         1 . A device, comprising:
 a replacement gate structure having a dished upper surface;   sidewall spacers positioned proximate said replacement gate structure; and   a gate cap layer positioned above said replacement gate structure, wherein said gate cap layer has a bottom surface that corresponds to said dished upper surface of said replacement gate structure.   
     
     
         2 . The device of  claim 1 , wherein said gate cap layer contacts said sidewall spacers. 
     
     
         3 . The device of  claim 1 , wherein an upper surface of said gate cap layer is a polished surface. 
     
     
         4 . The device of  claim 1 , wherein said dished upper surface of said replacement gate structure is a polished surface. 
     
     
         5 . The device of  claim 1 , wherein said dished upper surface defines a recess that has a peak depth within the range of about 5-15 nm. 
     
     
         6 . The device of  claim 1 , wherein said replacement gate structure is comprised of a high-k gate insulation layer and at least one metal layer positioned above said high-k gate insulation layer. 
     
     
         7 . The device of  claim 1 , wherein said sidewall spacers and gate cap layer are comprised of silicon nitride. 
     
     
         8 . The device of  claim 7 , further comprising a layer of silicon dioxide, wherein said sidewall spacers are positioned in said layer of silicon dioxide. 
     
     
         9 . A device, comprising:
 a replacement gate structure having a dished upper surface, wherein said dished upper surface is a polished surface;   sidewall spacers positioned proximate said replacement gate structure; and   a gate cap layer positioned above said replacement gate structure, wherein said gate cap layer contacts said sidewall spacers and wherein said gate cap layer has an upper surface that is a polished surface and a bottom surface that corresponds to said dished upper surface of said replacement gate structure.   
     
     
         10 . The device of  claim 9 , wherein said dished upper surface defines a recess that has a peak depth within the range of about 5-15 nm. 
     
     
         11 . The device of  claim 9 , further comprising a layer of silicon dioxide, wherein said sidewall spacers are positioned in said layer of silicon dioxide, and wherein said sidewall spacers and said gate cap layer are comprised of silicon nitride. 
     
     
         12 . A method, comprising:
 performing a first chemical mechanical polishing process to define a polished replacement gate structure having a dished upper surface; and   forming a gate cap layer above said polished replacement gate structure, wherein a bottom surface of said gate cap layer corresponds to said polished, dished upper surface of said polished replacement gate structure.   
     
     
         13 . The method of  claim 12 , wherein forming said gate cap layer comprises:
 forming a layer of gate cap material above said polished replacement gate structure; and   performing a second chemical mechanical polishing process on said layer of gate cap material.   
     
     
         14 . The method of  claim 12 , wherein said first chemical mechanical polishing process is a separate chemical mechanical polishing process from an initial chemical mechanical polishing process performed to initially define a replacement gate structure with a substantially planar upper surface. 
     
     
         15 . The method of  claim 12 , wherein said first chemical mechanical polishing process is a portion of an initial chemical mechanical polishing process performed to initially define a replacement gate structure. 
     
     
         16 . A method, comprising:
 forming a replacement gate structure in a gate opening defined by sidewall spacers positioned in a layer of insulating material;   performing a common etching process on at least said sidewall spacers and said layer of insulating material, wherein, after said common etching process is completed, an upper surface of said sidewall spacers is recessed relative to an upper surface of said layer of insulating material;   performing a first chemical mechanical polishing process to remove at least portions of said replacement gate structure that are positioned above said upper surface of said layer of insulating material and thereby define a polished replacement gate structure; and   after performing said first chemical mechanical polishing process, forming a gate cap layer above said polished replacement gate structure.   
     
     
         17 . The method of  claim 16 , wherein forming said gate cap layer comprises:
 forming a layer of gate cap material above said polished replacement gate structure; and   performing a second chemical mechanical polishing process on said layer of gate cap material.   
     
     
         18 . The method of  claim 16 , wherein said sidewall spacers are comprised of silicon nitride and said layer of insulating material is comprised of silicon dioxide. 
     
     
         19 . The method of  claim 16 , wherein said common etching process is performed using a C x H y F z  based etch chemistry. 
     
     
         20 . The method of  claim 19 , wherein said common etching process has been adjusted to provide etch selectivity between silicon nitride and silicon dioxide. 
     
     
         21 . The method of  claim 16 , wherein said replacement gate structure is exposed to said common etching process. 
     
     
         22 . The method of  claim 16 , wherein said polished replacement gate structure has a polished, dished upper surface and said gate cap layer has a bottom surface that corresponds to said polished, dished upper surface of said polished replacement gate structure. 
     
     
         23 . A method, comprising:
 forming a replacement gate structure in a gate opening defined by sidewall spacers positioned in a layer of insulating material;   performing a common etching process on at least said sidewall spacers and said layer of insulating material, wherein, after said common etching process is completed, an upper surface of said sidewall spacers is recessed relative to an upper surface of said layer of insulating material;   performing a first chemical mechanical polishing process to remove at least portions of said replacement gate structure that are positioned above said upper surface of said layer of insulating material and thereby define a polished replacement gate structure having a polished, dished upper surface;   after performing said first chemical mechanical polishing process, forming a layer of gate cap material above said polished replacement gate structure; and   performing a second chemical mechanical polishing process on said layer of gate cap material to define a gate cap layer that is positioned above said polished replacement gate structure, wherein said gate cap layer has a bottom surface that corresponds to said polished, dished upper surface of said polished replacement gate structure.   
     
     
         24 . The method of  claim 23 , wherein said common etching process is performed using a C x H y F z  based etch chemistry. 
     
     
         25 . The method of  claim 23 , wherein said common etching process has been adjusted to provide etch selectivity between silicon nitride and silicon dioxide. 
     
     
         26 . The method of  claim 23 , wherein said sidewall spacers and said gate cap layer are comprised of silicon nitride and said layer of insulating material is comprised of silicon dioxide.

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