Pll circuit

Abstract

A PLL circuit, for extracting phase error information from a demodulated signal in which a variance of a phase or an amplitude changes depending on a signal-to-noise power ratio, and providing negative feedback control, to thereby suppress a phase error of the demodulated signal, includes: a phase error detector for producing a phase error signal corresponding to a value of the phase error as the phase error information; a limiter circuit for limiting an expression range of the phase error signal to a constant value or less to produce the limited phase error signal; and a loop filter for producing a control signal based on the limited phase error signal to determine frequency characteristics.

1 .- 5 . (canceled) 
     
     
         6 . A clock synchronization circuit to be used in a 2 n -QAM demodulator, where n is an integer of 4 or more, the clock synchronization circuit comprising:
 a voltage-controlled oscillator producing a sampling clock signal in accordance with a control signal;   an A/D converter converting an analog baseband signal, which has been converted into a baseband by a quadrature demodulator, into a digital signal in synchronization with the sampling clock signal;   a phase error detector extracting, from the digital signal, a phase error corresponding to an optimum sampling phase of the analog baseband signal and the sampling clock signal to produce a phase error signal corresponding to a value of the phase error;   a limiter circuit limiting an expression range of the phase error signal to a constant value or less to produce the limited phase error signal; and   a loop filter producing, based on the limited phase error signal, the control signal so that the phase of the sampling clock signal matches with the optimum phase, to thereby determine frequency characteristics of a loop.   
     
     
         7 . A demodulator of a multilevel quadrature amplitude modulation scheme, which uses the clock synchronization circuit according to  claim 6 . 
     
     
         8 . A method for clock synchronization of a demodulator, comprising:
 producing a sampling clock signal in accordance with a control signal;   converting an analog baseband signal, which has been converted into a baseband by a quadrature demodulator, into a digital signal in synchronization with the sampling clock signal;   extracting, from the digital signal, a phase error corresponding to an optimum sampling phase of the analog baseband signal and the sampling clock signal;   producing a phase error signal corresponding to a value of the phase error;   limiting an expression range of the phase error signal to a constant value or less to produce the limited phase error signal; and   producing, based on the limited phase error signal, the control signal so that the phase of the sampling clock signal matches with the optimum phase, to thereby determine frequency characteristics of a loop.