General purpose embedded processor

Abstract

The invention provides an embedded processor architecture comprising a plurality of virtual processing units that each execute processes or threads (collectively, “threads”). One or more execution units, which are shared by the processing units, execute instructions from the threads. An event delivery mechanism delivers events—such as, by way of non-limiting example, hardware interrupts, software-initiated signaling events (“software events”) and memory events—to respective threads without execution of instructions. Each event can, per aspects of the invention, be processed by the respective thread without execution of instructions outside that thread. The threads need not be constrained to execute on the same respective processing units during the lives of those threads—though, in some embodiments, they can be so constrained. The execution units execute instructions from the threads without needing to know what threads those instructions are from.

1 . An embedded processor, comprising
 A. a plurality of processing units, each executing one or more processes or threads (collectively, “threads”),   B. one or more execution units that are shared by, and in communication coupling with, the plurality of processing units, the execution units executing instructions from the threads,   C. an event delivery mechanism that delivers events to respective threads with which those events are associated, wherein the event delivery mechanism
 i. is in communication coupling with the plurality of processing units, and 
 ii. delivers each such event to the respective thread without execution of instructions. 
   
     
     
         2 . The embedded processor of  claim 1 , wherein the thread to which an event is delivered processes that event without execution of instructions outside that thread. 
     
     
         3 . The embedded processor of  claim 1 , wherein the events include any of hardware interrupts, software-initiated signaling events (“software events”) and memory events. 
     
     
         4 . The embedded processor of  claim 1 , wherein the execution units execute instructions from the threads without need to know what thread they are from. 
     
     
         5 . The embedded processor of  claim 1 , wherein each thread is any of constrained or not constrained to execute on a same processing unit during a life of that thread. 
     
     
         6 . The embedded processor of  claim 1 , wherein at least one of the processing units is a virtual processing unit. 
     
     
         7 . An embedded processor, comprising
 A. a plurality of virtual processing units, each executing one or more processes or threads (collectively, “threads”), wherein each thread is any of constrained or not constrained to execute on a same processing unit during a life of that thread.   B. a plurality of execution units,   C. a pipeline control that is in communication coupling with the plurality of processing units and with the plurality of execution units, the pipeline control launching instructions from plural ones of the threads for concurrent execution on plural ones of the execution units,   D. an event delivery mechanism that is in communication coupling with the plurality of processing units and that delivers events to respective threads with which those events are associated without execution of instructions, where the events include any of hardware interrupts, software-initiated signaling events (“software events”) and memory events.   E. wherein a thread to which such an event is delivered processes that event without execution of instructions outside that thread.   
     
     
         8 . The embedded processor of  claim 7 , where the pipeline control comprises a plurality of instruction queues, each associated with a respective virtual processing unit. 
     
     
         9 . The embedded processor of  claim 8 , where the pipeline control decodes instruction classes from the instruction queues. 
     
     
         10 . The embedded processor of  claim 8 , where the pipeline control controls access by the processing units to a resource providing source and destination registers for the instructions dispatched from the instruction queues. 
     
     
         11 . The embedded processor of  claim 8 , wherein the execution units include a branch execution unit responsible for any of instruction address generation, address translation and instruction fetching. 
     
     
         12 . The embedded processor of  claim 11 , wherein the branch execution unit maintains state for the virtual processing units. 
     
     
         13 . The embedded processor of  claim 7 , where the pipeline control controls access by the virtual processing units to the execution units. 
     
     
         14 . The embedded processor of  claim 7 , where the pipeline control signals a branch execution unit that is shared by the virtual processing unit as the instruction queue for each virtual processing unit is emptied. 
     
     
         15 . The embedded processor of  claim 7 , where the pipeline control idles the execution units to decrease power consumption. 
     
     
         16 . The embedded processor of  claim 7 , wherein the plurality of execution units include any of integer, floating, branch, compare and memory units. 
     
     
         17 . An embedded processor system, comprising
 A. a plurality of embedded processors,   B. a plurality of virtual processing units executing on the plurality of embedded processors, each virtual processing executing one or more processes or threads (collectively, “threads”) and each virtual processing unit being any of constrained or not constrained to execute on a same virtual processing unit and/or a same processor during a life of that thread,   C. one or more execution units that are shared by, and in communication coupling with, the plurality of processing units, the execution units executing instructions from the threads, the execution units including any of integer, floating, branch, compare and memory execution units.   D. an event delivery mechanism that delivers events to respective threads with which those events are associated, wherein the event delivery mechanism
 i. is in communication coupling with the plurality of processing units, and 
 ii. delivers each such event to the respective thread without execution of instructions. 
   
     
     
         18 . The embedded processor system of  claim 17 , wherein the thread to which an event is delivered processes that event without execution of instructions outside that thread. 
     
     
         19 . The embedded processor system of  claim 18 , wherein the events include any of hardware interrupts, software-initiated signaling events (“software events”) and memory events. 
     
     
         20 . The embedded processor system of  claim 18 , wherein the branch unit is responsible for fetching instructions that are to be executed for the threads. 
     
     
         21 - 63 . (canceled)