Structure and method for topography free soi integration

Abstract

A semiconductor structure is provided that includes a semiconductor oxide layer having features. The semiconductor oxide layer having the features is located between an active semiconductor layer and a handle substrate. The semiconductor structure includes a planarized top surface of the active semiconductor layer such that the semiconductor oxide layer is beneath the planarized top surface. The features within the semiconductor oxide layer are mated with a surface of the active semiconductor layer.

What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 a semiconductor oxide layer having features located between an active semiconductor layer and a handle substrate, wherein the semiconductor oxide layer having features includes a non-planar surface being in direct contact with a surface of the active semiconductor layer and an opposing planar surface being in direct contact with an upper surface of the handle substrate.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein the active semiconductor layer includes silicon. 
     
     
         3 . The semiconductor structure of  claim 1 , wherein the active semiconductor layer includes silicon and carbon. 
     
     
         4 . The semiconductor structure of  claim 1 , wherein the active semiconductor layer includes quartz. 
     
     
         5 . The semiconductor structure of  claim 1 , wherein the active semiconductor layer has a planar top surface. 
     
     
         6 . The semiconductor structure of  claim 1 , wherein the semiconductor oxide layer includes silicon oxide. 
     
     
         7 . The semiconductor structure of  claim 1 , wherein the semiconductor oxide layer includes germanium oxide. 
     
     
         8 . The semiconductor structure of  claim 1 , wherein semiconductor oxide layer comprising a thermal oxide. 
     
     
         9 . The semiconductor structure of  claim 1 , wherein said features comprises raised portions and trench portions. 
     
     
         10 . The semiconductor structure of  claim 9 , wherein some of the raised portions have a different width. 
     
     
         11 . The semiconductor structure of  claim 10 , wherein some of the trench portions have a different width. 
     
     
         12 . A semiconductor structure, comprising:
 a semiconductor oxide layer having features, the semiconductor oxide layer located between an active semiconductor layer and a handle substrate, wherein the features of the semiconductor oxide layer are mated with a surface of the active semiconductor layer.   
     
     
         13 . The structure of  claim 12 , wherein the active semiconductor layer and the handle substrate are both comprised of silicon, and the semiconductor oxide layer is comprised of silicon oxide. 
     
     
         14 . The semiconductor structure of  claim 12 , wherein the active semiconductor layer includes silicon. 
     
     
         15 . The semiconductor structure of  claim 12 , wherein the active semiconductor layer includes silicon and carbon. 
     
     
         16 . The semiconductor structure of  claim 12 , wherein the active semiconductor layer includes quartz. 
     
     
         17 . The semiconductor structure of  claim 12 , wherein the active semiconductor layer has a planar top surface. 
     
     
         18 . The semiconductor structure of  claim 12 , wherein the semiconductor oxide layer includes germanium oxide. 
     
     
         19 . The semiconductor structure of  claim 12 , wherein said features comprises raised portions and trench portions. 
     
     
         20 . The semiconductor structure of  claim 19 , wherein some of the raised portions have a different width, and wherein some of the trench portions have a different width.